Functional Description -- HPC II Controller, External Memory ... - Altera

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5-24 Local Interface Signals emi_rm_004 2013.12.16 Signal Name avl_ready (12) local_refresh_ ack local_self_ rfsh_ack local_power_ down_ack ecc_ interrupt (13) Direction Output Output Output Output Output Description The avl_ready signal indicates that the controller is ready to accept request signals. If controller asserts the avl_ready signal in the clock cycle that it asserts a read or write request, the controller accepts that request. The controller deasserts the avl_ready signal to indicate that it cannot accept any more requests. The controller can buffer eight read or write requests, after which the avl_ready signal goes low. The avl_ready signal is deasserted when any of the following are true: • The Timing bank Pool is full. • The FIFO register that stores read data from the memory device is full. • The write data FIFO register is full. • The controller is waiting for write data when in ECC mode. Refresh request acknowledge, which the controller asserts for one clock cycle every time it issues a refresh. Even if you do not turn on Enable User Auto-Refresh Controls, local_refresh_ack still indicates to the local interface that the controller has just issued a refresh command. Self refresh request acknowledge signal. The controller asserts and deasserts this signal in response to the local_self_rfsh_req signal. Auto power-down acknowledge signal. The controller asserts this signal for one clock cycle every time auto power-down is issued. Interrupt signal from the ECC logic. The controller asserts this signal when the ECC feature is turned on, and the controller detects an error. Altera Corporation Functional Description—HPC II Controller Send Feedback
emi_rm_004 2013.12.16 Controller Interface Signals 5-25 Signal Name Direction Description Notes to Table: 1. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_addr becomes a per port value, avl_addr_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 2. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_be becomes a per port value, avl_be_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 3. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_burstbegin becomes a per port value, avl_burstbegin_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 4. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_read_req becomes a per port value, avl_read_req_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 5. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_size becomes a per port value, avl_size_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 6. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_wdata becomes a per port value, avl_wdata_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 7. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_write_req becomes a per port value, avl_write_req_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 8. This signal is not applicable to the hard memory controller. 9. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_rdata becomes a per port value, avl_rdata_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 10. This signal is not applicable to the hard memory controller. 11. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_rdata_valid becomes a per port value, avl_rdata_valid_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 12. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_ready becomes a per port value, avl_ready_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab. 13. This signal is not applicable to the hard memory controller. Controller Interface Signals The following table lists the controller interface signals. Functional Description—HPC II Controller Altera Corporation Send Feedback
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