Functional Description -- HPC II Controller, External Memory ... - Altera

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5-2 HPC II Memory Controller Architecture Figure 5-1: High-Level Diagram of Memory Interface Architecture emi_rm_004 2013.12.16 Memory Interface IP Memory Controller PHY Data Master Avalon-MM or AXI Converter Avalon-ST Interface AFI Interface AFI Interface External Memory CSR Interface CSR Master HPC II Memory Controller Architecture The memory controller logic block uses an Avalon Streaming (Avalon-ST) interface as its native interface, and communicates with the PHY layer by the Altera PHY Interface (AFI). The following figure shows a block diagram of the memory controller architecture. Altera Corporation Functional Description—HPC II Controller Send Feedback
emi_rm_004 2013.12.16 Figure 5-2: Memory Controller Architecture Block Diagram HPC II Memory Controller Architecture 5-3 Memory Controller Rank Timer Avalon-ST Input Interface Command Generator Write Data Buffer Timing Bank Pool Arbiter ECC AFI Interface to PHY Read Data Buffer CSR Interface Avalon-ST Input Interface The Avalon-ST interface serves as the entry point to the memory controller, and provides communication with the requesting data masters. For information about the Avalon interface, refer to Avalon Interface Specifications. AXI to Avalon-ST Converter The HPC II memory controller includes an AXI to Avalon-ST converter for communication with the AXI protocol. The AXI to Avalon-ST converter provides write address, write data, write response, read address, and read data channels on the AXI interface side, and command, write data, and read data channels on the Avalon-ST interface side. Handshaking The AXI protocol employs a handshaking process similar to the Avalon-ST protocol, based on ready and valid signals. Command Channel Implementation Functional Description—HPC II Controller Altera Corporation Send Feedback
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Functional Description -- HPC II Controller, External Memory ... - Altera

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