Functional Description -- HPC II Controller, External Memory ... - Altera

5-24
Local Interface Signals
emi_rm_004
2013.12.16
Signal Name
avl_ready (12)
local_refresh_
ack
local_self_
rfsh_ack
local_power_
down_ack
ecc_
interrupt (13)
Direction
Output
Output
Output
Output
Output
Description
The avl_ready signal indicates that the controller is ready to accept
request signals. If controller asserts the avl_ready signal in the
clock cycle that it asserts a read or write request, the controller accepts
that request. The controller deasserts the avl_ready signal to
indicate that it cannot accept any more requests. The controller can
buffer eight read or write requests, after which the avl_ready signal
goes low.
The avl_ready signal is deasserted when any of the following are
true:
• The Timing bank Pool is full.
• The FIFO register that stores read data from the memory device is
full.
• The write data FIFO register is full.
• The controller is waiting for write data when in ECC mode.
Refresh request acknowledge, which the controller asserts for one clock
cycle every time it issues a refresh. Even if you do not turn on Enable
User Auto-Refresh Controls, local_refresh_ack still indicates
to the local interface that the controller has just issued a refresh
command.
Self refresh request acknowledge signal. The controller asserts and
deasserts this signal in response to the local_self_rfsh_req
signal.
Auto power-down acknowledge signal. The controller asserts this
signal for one clock cycle every time auto power-down is issued.
Interrupt signal from the ECC logic. The controller asserts this signal
when the ECC feature is turned on, and the controller detects an error.
Altera Corporation
Functional Description—HPC II Controller
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