Functional Description -- HPC II Controller, External Memory ... - Altera

5-18
Local Interface Signals
emi_rm_004
2013.12.16
Name
soft_reset_n
seriesterminationcontrol
parallelterminationcontrol
oct_rdn
oct_rup
dqs_delay_ctrl_import
csr_clk
Direction
Input
Input (for
OCT slave)
Output (for
OCT master)
Input (for
OCT slave)
Output (for
OCT master)
Input (for
OCT master)
Input (for
OCT master)
Input
Output
Description
Edge detect reset input for control by other
system reset logic. Assert to cause a complete
reset to the PHY, but not to the PLL that the
PHY uses.
Required signal for PHY to provide series
termination calibration value. Must be
connected to a user-instantiated OCT control
block (alt_oct) or another UniPHY instance
that is set to OCT master mode.
Unconnected PHY signal, available for
sharing with another PHY.
Required signal for PHY to provide series
termination calibration value. Must be
connected to a user-instantiated OCT control
block (alt_oct) or another UniPHY instance
that is set to OCT master mode.
Unconnected PHY signal, available for
sharing with another PHY.
Must connect to calibration resistor tied to
GND on the appropriate RDN pin on the
device. (Refer to appropriate device
handbook.)
Must connect to calibration resistor tied to
Vccio on the appropriate RUP pin on the
device. (See appropriate device handbook.)
Allows the use of DLL in another PHY
instance in this PHY instance. Connect the
export port on the PHY instance with a
DLL to the import port on the other PHY
instance.
Clock for the configuration and status register
(CSR) interface, which is the same as afi_
clk and is always synchronous relative to
the main data slave interface.
Note:
1. Applies only to the hard memory controller with multiport front end available in Arria V and Cyclone V
devices.
Local Interface Signals
The following table lists the controller local interface signals.
Altera Corporation
Functional Description—HPC II Controller
Send Feedback