13th International Conference on Membrane Computing - MTA Sztaki

T. Hinze, B. Schell, M. Schumann, C. Bodenstein
output variable setting. In case of a NOR gate, the transition table results in
the following set of reactions:
a b c corresponding reactions
0 0 1 C F + A F + B F k
−→ C T + A F + B F
0 1 0 C T + A F + B T k
−→ C F + A F + B T
1 0 0 C T + A T + B F k
−→ C F + A T + B F
1 1 0 C T + A T + B T k
−→ C F + A T + B T
In order to maintain a high signal quality, we equip each chemical logic gate
of output c with two additional reactions of the form C T +2C F −→ km
3C F and
C F +2C T −→ km
3C T . All together, mass-action kinetics lead to the ODEs:
Ȧ F =0; Ȧ T =0; Ḃ F =0; Ḃ T =0;
Ċ T = kC F A F B F + k m C F (C T ) 2 − k m C T (C F ) 2
Ċ F = kC T A F B T + kC T A T B F + kC T A T B T + k m C T (C F ) 2 − k m C F (C T ) 2
Analogously, all types of binary logic gates can be transferred into corresponding
chemical representations. Please note that each chemical logic gate owns a certain
latency determined by the rate constants k and k m due to the amount of time
necessary to switch the output concentrations. Taking into account this latency,
chemical logic gates of the aforeintroduced form are sufficient to be cascaded in
a way that a gate’s output might serve as input for a subsequent gate.
For setting up a binary counter modulo 17, we need to distinguish 17
states, which requires five bits per state. The counting is organised in a way
that a periodical clock signal serves as a trigger initiating a state transition
(b 1 ,...,b 5 ) ↦→ (b ′ 1,...b ′ 5). To this end, we utilise a five-bit Gray code, which
keeps the total number of logic gates low since almost all state transitions proceed
by changing one out of five bits:
count b 1 b 2 b 3 b 4 b 5 b ′ 1 b ′ 2 b ′ 3 b ′ 4 b ′ 5 count b 1 b 2 b 3 b 4 b 5 b ′ 1 b ′ 2 b ′ 3 b ′ 4 b ′ 5
1 0 0 0 0 0 0 0 0 0 1 10 0 1 1 0 1 0 1 1 1 1
2 0 0 0 0 1 0 0 0 1 1 11 0 1 1 1 1 0 1 1 1 0
3 0 0 0 1 1 0 0 0 1 0 12 0 1 1 1 0 0 1 0 1 0
4 0 0 0 1 0 0 0 1 1 0 13 0 1 0 1 0 0 1 0 1 1
5 0 0 1 1 0 0 0 1 1 1 14 0 1 0 1 1 0 1 0 0 1
6 0 0 1 1 1 0 0 1 0 1 15 0 1 0 0 1 0 1 0 0 0
7 0 0 1 0 1 0 0 1 0 0 16 0 1 0 0 0 1 1 0 0 0
8 0 0 1 0 0 0 1 1 0 0 17 1 1 0 0 0 0 0 0 0 0
9 0 1 1 0 0 0 1 1 0 1
Bit b 1 indicates the accumulation of 17 counts constituting the counter’s output.
In addition, intermediate states need to be temporarily stored in order to bridge
the time span between successive counts. To this end, we incorporate five RS flip
flops into the counter automaton, each of which is composed of two regeneratively
coupled NOR gates, see Figure 5. For bitwise state transition, we utilise five
boolean functions resulting from the transition table above and syntactically
simplified using standard Karnaugh optimisation. We denote these functions in
disjunctive normal form:
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