13th International Conference on Membrane Computing - MTA Sztaki

Fast hardware implementations of P systems
– System 4 (opposite), 1 ≤ i ≤ N
r i :
{
o i−1 o i → o i o i+1 i mod 2 = 0
o i o i+1 → o i o i−1 otherwise
For each of four types a system with N equal to 10, 20 and 50 was considered
with the initial multiplicity of all objects equal to one. Then for each obtained
system 1024 executions of 8192 transitions have been carried out. Each execution
differs from the others by the seed required by the random number generator in
the initialization stage. In consequence, different values are obtained during the
assignment stage, which results in different executions. As results of experiments
following values are collected: the cardinality of objects in the last configuration,
the seed of the random number generator and the number of steps to reach the
halting configuration if the system reached it.
The target circuit for executions was the Xilinx Virtex-5 XC5VFX70T, code
for different P systems were generated by a Java software and this code was synthesised,
placed and routed using Xilinx tools. Since the input/output interface
has not been developed yet, ChipScope, a Xilinx’s debug tool has been used.
This tool let us, synchronously, change and capture the above values directly
from the FPGA.
Table 1 shows hardware resource consumption and clock rate in MHz of the
system without the debug logic. The implementation achieves high performance,
with frequencies higher than 100 MHz, i.e., it permits to simulate around 2 ×
10 7 computational steps per second. On the other hand, the hardware resource
consumption depends only on the number of rules. This is coherent with the fact
that rules of all systems do not change the total number of objects and share
the same dependency graph.
Table 1. Hardware resource consumption and clock rate of hardware implementation.
Type Size (Nb. of rules) Slices LUTs BRAMs Clock rate
Circular
2-circular
Linear
Opposite
10 2 % 2 % 1 % 120.02 MHz
20 6 % 10 % 1 % 101.44 MHz
50 41 % 31 % 1 % 100.68 MHz
10 2 % 2 % 1 % 120.02 MHz
20 7 % 6 % 1 % 110.77 MHz
50 37 % 31 % 1 % 100.44 MHz
10 2 % 2 % 1 % 120.02 MHz
20 10 % 6 % 1 % 100.56 MHz
50 40 % 31 % 1 % 100.85 MHz
10 2 % 2 % 1 % 120.02 MHz
20 7 % 6 % 1 % 105.73 MHz
50 37 % 31 % 1 % 100.89 MHz
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