13th International Conference on Membrane Computing - MTA Sztaki

Fast hardware implementations of P systems
6 Conclusions
In this article we presented a new design for a fast hardware implementation
of a simulator for P systems. The obtained circuit permits to simulate a nondeterministic
computational step of the system in a constant time (5 clock cycles).
Hence, the obtained simulator achieves a high performance that is close to
the maximal possible value (one cycle per step). The key point of our approach
is the representation of the sequences of all possible rule applications as words
of some regular or non-ambiguous context-free language. In this case using the
generating series for the corresponding language it is possible to generate functions
that precompute all possible rule applications. It is worth to note that the
speed of the computation does not depend on the number of rules. However,
there is a dependency between this number and the space on the chip. With the
used board it is possible to simulate P systems having up to 100 rules.
We exemplified our approach by an FPGA implementation of different P
systems working in maximal set mode with rules dependency graph in a form of
a chain. We obtained a speed of about 2 × 10 7 computational steps per second.
Our different tests showed that the computation is non-deterministic and that
the values of the parameters have expected mean values.
As a future research we plan to develop a software that will allow us to generate
the hardware design in an automatical way based on the regular language
describing the rules joint applicability.
The design described in this article is quite generic and does not use many
features of FPGA. Therefore, it could be interesting to use the presented method
for the speed-up of the existing software simulators of P systems.
Acknowledgements
This work has been partially supported by the Ministerio de Ciencia e Innovación
of the Spanish Government under project TEC2011-27936 (HIPERSYS),
by the European Regional Development Found (ERDF) and by the Ministry of
Education of Spain (FPU grant AP2009-3625).
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