13th International Conference on Membrane Computing - MTA Sztaki

S. Verlan, J. Quiros
the present configuration. In order to update it, each register add up its content
and values generated by previous core. Besides that, this core rises a control
signal when current configuration is equal to previous one, i.e., it indicates that
system has reached a stop condition to unit control.
Unit Control and Output Interface
Besides previous cores, an additional block, called controlBlock, is required to
provide communication and control logic. Control is implemented using a finite
state machine, which requires five states, and it generates all control signals.
Although input/output interface has not been developed yet, some debug cores
are used to control execution and get results.
In conclusion, the proposed hardware design requires only five clock cycles
per iteration, which is a good achievement, although the final speed depends on
the relation cycles-frequency. Our design takes advantages of FPGA technology
and the implementation achieves a high degree of parallelism of objects in the
initial stage, and of rules in the others. However, the key of system’s performance
is the implementation of the automaton in the assignment stage. All operations
required to compute NBV ariants(Π, C, smax) and V ariant(n, Π, smax) are
defined recursively and can be pipelined. In assignRule, each sub-block associated
to n-th rule computes, asynchronously, the value of N (associated to its
rule), basing on values obtained by previous block. This permits to execute all
operations in only two cycles, one for left propagation and another for right
propagation, while a synchronous version requires, at least, n cycles.
4.3 Experimental Results
We tested the design on a series of concrete examples. All of them consider rules
whose dependency graph forms a chain, the difference being in the right-hand
side. We consider four P systems with the alphabet O = {o 0 , . . . , o N }, N > 0
and having following rules (we consider index operations modulo N + 1):
– System 1 (circular)
r i :
– System 2 (2-circular)
{
o i−1 o i → o i o i+1 1 ≤ i < N − 1
o N−1 o N → o 0 o 1 i = N
r i : o i−1 o i → o i+1 o i+2 ,
1 ≤ i ≤ N
– System 3 (linear)
r i :
{
o i−1 o i → o i o i+1 1 ≤ i < N − 1
o N−1 o N → o N o N i = N
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