13th International Conference on Membrane Computing - MTA Sztaki

S. Verlan, J. Quiros
digital FPGA circuit synchronized by a global clock signal, in one cycle of FPGA
it is possible to compute any functions whose implementation has a delay which
does not exceed the period of the global clock signal. A pipeline using arithmetical
operations and, in general, any combinatorial and sequential asynchronous
subsystems, are usually included in this group.
In order to simplify the problem we split it into two parts corresponding to
the construction of following recursive functions:
NBV ariants(Π, C, δ):
gives the cardinality of the set Appl(Π, C, δ)
V ariant(n, Π, C, δ), where 1 ≤ n ≤ NBV ariants(Π, C, δ):
gives the multiset of rules corresponding to the n-th element of some initially
fixed enumeration of Appl(Π, C, δ).
It is clear that if each function is computed in constant time, then the multiset
of rules to be applied can also be computed in a constant time. In what follows
we will discuss methods for the construction of these two functions for different
classes of P systems.
In the following we will need the notion of the rules’ dependency graph. This
is a weighted bipartite graph where the first partition U contains a node labeled
by a for each object a of Π, while the second partition V contains a node labeled
by r for each rule r of Π. There is an edge between a node r ∈ V and a node
a ∈ U labeled by a weight k if a k ∈ lhs(r) (and a k+1 ∉ lhs(r).
Example 2. Consider a P system Π 1 having two rules r 1 : ab → u and r 2 : bc →
v. These rules have the following dependency graph:
r 1
❄
r 2
❄❄❄❄❄❄
❄ 8 ❄❄❄❄❄❄❄
7 777777 8 8888 a
b
c
Let N a , N b and N c be the number of objects a, b and c in a configuration C.
We define
N 1 = min(N a , N b )
N 2 = min(N b , N c )
N = min(N 1 , N 2 )
Suppose that Π evolves in a maximally parallel derivation mode. Then the
set Appl(Π, C, max) can be computed as follows:
Appl(Π, C, max) =
⋃ { }
r p+k1
1 r q+k2
2 ,
p+q=N
where k j = N j ⊖ N, 1 ≤ j ≤ 2, where ⊖ is the positive subtraction operation.
From this representation it is clear that NBV ariants(Π, C, max) = N + 1,
which can be computed in constant time on FPGA.
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