13th International Conference on Membrane Computing - MTA Sztaki

<strong>13th</strong> <strong>International</strong> <strong>Conference</strong> on Membrane Computing, CMC13,
Budapest, Hungary, August 28 - 31, 2012. Proceedings, pages 433 - 452.
Fast Hardware Implementations of P Systems
Sergey Verlan 1 and Juan Quiros 2
1 LACL, Département Informatique, Université Paris Est,
61, av. Général de Gaulle, 94010 Créteil, France
Email: verlan@univ-paris12.fr
2 ID2 Group, Department of Electronic Technology, University of Sevilla,
Avda. Reina Mercedes s/n, 41012, Sevilla, Spain
Email: jquiros@dte.us.es
Abstract. In this article we present the design of a fast hardware simulator
for P systems using the field-programmable gate array (FPGA)
technology. The simulator is non-deterministic and it uses a constant
time procedure to choose one of the computational paths. The obtained
strategy is fair and it is based on a pre-computation of all possible rule
applications. This pre-computation is obtained by using the representation
of all possible multisets of rules’ applications as context-free languages.
Then using a standard technique involving formal power series
it is possible to obtain the generating series of corresponding languages
that permits to construct the structure representing all possible rule applications
for any configuration. We give a hardware design implementing
some concrete examples and present the obtained results which feature
an important speed-up.
1 Introduction
The problem of computer simulation of different variants of P systems arose at
the early beginning of the development of the area. The first software simulators
[5, 16] were quite inefficient, but they provided an important understanding
of the related problems. Since most variants of P systems are by definition inherently
parallel and non-deterministic, it is natural to use distributed or parallel
architectures in order to achieve better performances [1, 17, 6].
Another fruitful idea is to use specialized hardware for the simulation and this
approach was realized in [14, 11] using FPGA reconfigurable hardware technology.
The first implementation from [14] has the design based on region processors
which have rules as instructions and multiplicity of objects as data. Although
it has several limitations, it demonstrates that P systems can be executed on
FPGAs. In the other approach [8, 10] two possible designs are detailed: ruleoriented
and region-oriented systems. In the first one, each rule is considered as
a basic processing unit and, in consequence, has a specific hardware core. As
a result, system achieves maximum degree of parallelism, due to all rules are
executed in parallel by specific hardware components. In the second case the basic
processing unit are regions. Thus, communications between regions acquire
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