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reduction. However, our first contribution shows
that, the memory size for the state metrics can
be reduced by 40% by a normalization of the state
metrics without a significant loss of
performance.
Moreover, we have proposed an efficient way to
reduce the dynamic power dissipation in the
turbo decoder. This technique is based on a
dynamic re-encoding of the received messages.
The idea is to decrease the state transition
activity of the trellis-based algorithms by
replacing the classical direct decoding of the
random noisy codewords by an equivalent
decoding of an almost “all zero” codewords in
order to keep the survivor path on the “zero
path”.
Simulation results showed that the state
transition activity of the turbo decoding process
is thus significantly reduced with no performance
degradation. The design and the prototyping of a
turbo decoder dedicated to the UMTS standard
based on the proposed technique and a method
to reduce the state metric quantization has been
done. The objective was to measure the total
power dissipation of the circuit.
3. Algorithm-Architecture-
Matching approach applied to a
iterative receiver for MIMO system
The information theoretical analysis of MIMO
(Multiple Input Multiple Output) systems
promises large capacity gains compared with
conventional SISO (Single Input Single Output)
system. A promising technique to achieve
benefits such as higher data rate and improved
link reliability is to utilize a full rate full diversity
space-time (FR-FD ST) code. We will focus on
one of them that deals with the association of
linear precoding and spatial multiplexing. The
presence of Forward Error Correcting (FEC) code
in most of standardized systems allows the
designer to take advantage of channel decoding
by carrying out the turbo principle. In the context
of transmission systems with interference, such
an iterative receiver, known as turbo equalizer or
turbo detector, achieves remarkable gains in
BER performance, compared with a non iterative
scheme. However, to design a high throughput,
low complexity, and low latency architecture for
an iterative receiver is a hard issue that slows
down the technology transfer toward industry.
We have proposed an architectural design of an
iterative receiver for linearly precoded MIMO
systems. The architectural exploration is driven
by the limitation of the complexity and the FER
performance. A new formulation of the MMSE
algorithm has been considered to decrease the
complexity of the SISO equalizer without error
rate performance degradation. In order to reduce
the memory required by the 64-state SISO
decoder, the window sliding principle was
applied. In addition, a particular block interleaver
was proposed as an alternative to the random
interleaver. However, the interleaving design rule
imposes a latency which has an impact on the
whole receiver. In order to obtain efficient
exchange data process between the SISO
equalizer and the SISO decoder, new interleaving
design rules have to be investigated. The
proposed architectural solution has been
designed for a programmable target (FPGA) and
implemented onto a prototyping board. The real
time prototype demonstrate the performance of
the proposed iterative receiver for MIMO
systems.
4. Designing a generic single-chip
multiprocessor architecture for
turbo-communication
Applications in the field of digital
communications are becoming more and more
diversified and complex. This trend is driven by
the emergence of turbo-communications which
generalize the principle of iterative processing
introduced by the turbo-codes. Implementation
of turbo-communication systems, so-called
turbo-receivers, is becoming crucial to reach the
nowadays performance requirements in terms of
transmission quality. Several dedicated
implementations of these systems have already
been proposed. However, implementation
requirements in flexibility (to support the
continuously developing new standards and
applications in this field) and in high-throughput,
make resorting to new design methodologies and
the proposal of a flexible turbo communication
platform inevitable.
The subject of this project deals with the
implementation of a generic multiprocessor
platform dedicated to turbo-receivers et more