researResearch - Télécom Bretagne
researResearch - Télécom Bretagne
researResearch - Télécom Bretagne
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<strong>researResearch</strong><br />
A de Bruijn network, based on the de Bruijn<br />
graph, was chosen due to its appropriateness to<br />
support the communications of a multiprocessor<br />
LDPC/turbo decoder. In fact, the structure of the<br />
network allows any permutation to be routed<br />
efficiently thanks to the path diversity offered by<br />
the network. The conflicting memory accesses<br />
are alleviated because the conflicting packets<br />
can be deviated appropriately until they attain the<br />
targeted processor rather than being blocked or<br />
buffered. In addition, the logarithmic diameter of<br />
the network (log2(N) leads to small latencies and<br />
the number of routers is reduced because it is a<br />
direct network. We developed the topology and<br />
the network architecture, the packet format as<br />
well as the routers and the network interfaces.<br />
We have also proposed to use priorities specific<br />
to LDPC and turbo codes for the arbitration of<br />
conflicting packets. The unique trade-off<br />
between flexibility and performance (scalability,<br />
frequency, area) offered by the de Bruijn network<br />
demonstrates its efficiency in the context of a<br />
flexible parallel channel decoder supporting<br />
LDPC and turbo codes. We are now working to<br />
extend the proposed NoC architecture towards<br />
further turbo-communication applications.<br />
Publications<br />
Articles in a peer-review journals<br />
[1] Raphaël Le Bidan, Camille Leroux, Christophe Jégo,<br />
Ramesh Pyndiah, Patrick Adde, “Reed-Solomon turbo<br />
product codes for optical communications : from code<br />
optimization to decoder design”, EURASIP journal on<br />
wireless communications and networking, April 2008, vol.<br />
2008, pp. 1-14.<br />
[2] Saeed Sharifi Tehrani, Christophe,Jégo, Zhu Bo, Warren<br />
Gross, “Stochastic decoding of linear block codes with<br />
high-density parity-check matrices”, IEEE transactions on<br />
signal processing, November 2008, vol. 56, n°11, pp.<br />
5733-5739.<br />
[3] Olivier Muller, Amer Baghdadi, Michel Jézéquel, “From<br />
parallelism levels to a multi-ASIP architecture for turbo<br />
decoding”, IEEE transactions on very large scale<br />
integration (VLSI) systems, January 2009, vol. 17, n° 1, pp.<br />
92-102<br />
54
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