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RESEARCH
specifically to convolutional turbo decoders.
Thus, the subject evolves around two research
areas: algorithmical aspects of turbo-decoding
systems and architectural aspects of their
numeric design.
Concerning the algorithmical part, this work
presents a wide range of investigations of
parallelism in convolutional turbo decoding.
These investigations are based on three-level
classification of parallelism techniques, which is
constructed according to their granularity and
acceleration abilities. Analysis of this
classification reveals that sub-block parallelism
and component-decoder parallelism need efforts
to improve the implementation efficiency. Our
researches enlighten that sub-block parallelism
becomes more efficient with the message
passing initialisation technique. Additionally, we
show that component-decoder parallelism with
shuffled decoding improves the efficiency of
highly parallelized turbo-decoder architecture.
Furthermore, we present how to optimise this
efficiency through constraints interleaver design.
Concerning the architectural part, algorithmical
results were integrated in a multiprocessor
platform exploiting the tradeoffs between
hardware and software (i.e.
performance/flexibility) at processing and
communication levels. To cope with processing
tradeoffs, we propose a Application-Specific
Instruction-set Processor (ASIP) dedicated to
turbo-decoding of convolutional codes. The
designed ASIP provides the required flexibility
while enabling high-throughput thanks to a
highly parallelized datapath. At the
communication level, our multi-ASIP platform
exploits dedicated network on chip in order to
ensure the bandwidth required for iterative
exchange of information. The resulting multi-
ASIP platform was prototyped on emulation
board based on FPGA.
The flexibility of the proposed platform enables
the support of all existing and emerging
standards of convolutional turbo-codes, and have
industrial applications in mobile and satellitebased
communications, broadcasting, Internet
high-throughput.
5. Adaptive Network-on-Chip
Architecture Design for Turbo-
Receivers
Multiprocessor platforms constitute a promising
architectural solution for the design of highthroughput
flexible turbo-receivers. Besides
application algorithm optimizations and
application-specific processor design, the onchip
communication network connecting the
multiple on-chip cores constitutes a major issue.
Conventional on-chip buses become inefficient in
large systems and the nanotechnology
integration issues (propagation delay, crosstalk,
etc.) make their use no more practical. In this
context, Network-on-Chip has recently emerged
as a new paradigm allowing to cope with these
major design issues. It consists of adapting the
modular, scalable, and flexible
hardware/software architectures and design
tools of Network domain to the context of silicon
integration.
Our aim in this project is to propose an adaptive
network-on-chip architecture allowing efficient
multiprocessor turbo-receiver implementation.
The proposed NoC architecture should efficiently
accommodates the intensive and random
extrinsic information exchange between the
iterative processing components. It should
enable communication-resource management
and adapt according to the application mode or
standard, environment, and QoS requirements.
In this context, appropriate application-specific
NoC topologies, routing algorithms, resource
management techniques, and software network
layers are being proposed. On-chip
communications can be designed while applying
a completely ad hoc methodology or with generic
bus-based or NoC-based solutions. The first one
provides dedicated optimal solution but does not
offer the flexibility required by industry for
reprogramming, standard updates or IP reuse.
The second approach is flexible but can lead to
over-sized solutions, which are not acceptable
for cost and energy reasons. Most of current NoC
are firstly designed independently from
applications, and in a second step they are
tailored to meet application constraints. Our
approach in this research thematic is firstly
based on application analysis.
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