Apalis Carrier Board Design Guide - Toradex

Apalis Carrier Board Design GuideSPI ModeClockPolarityClockPhaseDescription0 0 0 Clock has positive polarity and the data is latched at the positive edge of SCK1 0 1 Clock has positive polarity and the data is latched at the negative edge of SCK2 1 0 Clock has negative polarity and the data is latched at the positive edge of SCK4 1 1 Clock has negative polarity and the data is latched at the negative edge of SCKTable 27: SPI Modes2.14.1 SPI SignalsA SPI bus consists of one master and one or many slaves. In the Apalis standard, the module is theSPI master. Some modules may also allow themselves to be used as SPI slaves. Some modules mayprovide this function on different, non-standard pins.ApalisPinApalisSignal NameI/OTypePowerRailDescription225 SPI1_MOSI O CMOS 3.3V Master Output, Slave Input223 SPI1_MISO I CMOS 3.3V Master Input, Slave Output227 SPI1_CS O CMOS 3.3V Slave Select221 SPI1_CLK O CMOS 3.3V Serial Clock231 SPI2_MOSI O CMOS 3.3V Master Output, Slave Input229 SPI2_MISO I CMOS 3.3V Master Input, Slave Output233 SPI2_CS O CMOS 3.3V Slave Select235 SPI2_CLK O CMOS 3.3V Serial ClockTable 28: SPI Signals2.14.2 Unused SPI Signal TerminationUnused SPI signals can be left unconnected.2.15 CANThe controller area network (CAN) bus is a multi-master serial bus standard. It was first introducedfor the automotive sector and soon became widely adopted in the industrial sector. Differentversions of CAN specifications are available. Make sure that the corresponding Apalis modulecomplies with the required version.2.15.1 CAN SignalsApalisPinApalisSignal NameI/OTypePowerRailDescription14 CAN1_TX O CMOS 3.3V CAN port 1 transmit pin12 CAN1_RX I CMOS 3.3V CAN port 1 receive pin18 CAN2_TX O CMOS 3.3V CAN port 2 transmit pin16 CAN2_RX I CMOS 3.3V CAN port 2 receive pinTable 29: CAN SignalsToradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com Page | 53