Proceedings with Extended Abstracts (single PDF file) - Radio ...

DEVELOPMENT OF A DIGITAL RECEIVER FOR THE JICAMARCAOBSERVATORY RADARSGabriel Michhue and Ronald F. WoodmanJicamarca Radio Observatory, Instituto Geofísico del Perú, Lima, PeruThe large proliferation of cellular telephones and services has made available very powerfuldigital receivers at a very economical price. This has open the possibility to modernize thereceivers used at the Jicamarca Observatory, using this technique, for all of the radarscurrently in use at the observatory, including the IS radar, JULIA, the Antarctic MST and theSOUSY radar. The receivers are flexible enough and they could be used for other radioexperiments with a simple change of front end and/or receiver local oscillator.The approach taken was to develop our own, but rather than building the receiver using ourown integration of commercially available chips, we have taken advantage of the existence ofcompatible evaluation boards for the 12-bit ADC, sampling at RF frequency speeds, and anevaluation board for the digital receiver proper. This may had not been the propereconomical approach if we were to produce a large number of units, but for a limitedproduction, it has allowed us to reduce the development time and engineering effort. Ourdevelopment effort has been limited to the development of the receivers interface to aNational Instruments PCI PC digital interface and the associated data acquisition software.On figure 1 we show a schematic diagram of the receiving system. In this case we showversion 1, for two receivers; the minimum required for most of the IS experiments. We usean Analog Devices AD6620 Digital receiver evaluation board. This board uses the PCparallel port for receiver configuration setup and for data taking. The low speed of theparallel port is not a limitation for the configuration function but it is too slow for data taking.Fortunately, the board has a direct access to the parallel data output of the digital receiverchip which is connected directly to the PCI interface. Independent configuration of the tworeceivers is performed through the parallel port. This port also allows us to use themanufacturer’s software for receiver evaluation tasks that do not require high speed. In thisversion the two 16-bit data outputs of the two receivers are concatenated to produce 32-bitoutput, which is connected to a National Instruments PCI board through a 64KWord FIFO,which is part of our interface board. We can achieve in this way a maximum throughput of80 Mega samples/sec, much higher than required by the maximum bandwidth (BW) of thetransmitter/antenna and analog receiving front end.The antenna signals are passed through a 25dB gain analog front end with a BW of 4MHz.The analog filter has a sharp cut-off and is used to reject any RF interference before thesampling and digital filtering operations. Sampling is performed at 64MHz, which effectivelybeats the 50MHZ signal to an aliased –32 to +32 MHz window with a center frequency of14Mhz. Sampling is performed in an AD6640 12-bit analog to digital converter. TheAD6620 digital receiver schematic is shown in figure 2. The 14 MHz is converted there tobase band, it is then filtered and decimated by the three internal filters of the AD6620 unit.The first two cascaded integrated comb (CIC) filters are used to reject further undesiredfrequencies and reduced the sampling rate to a convenient rate (~4MHz). Final hardwarefiltering is performed in the third unit ram coefficient finite impulse response (RCF) filter, aprogrammable 256 register FIR filter which as such has a large flexibility to produce almostany desired BW shape, including exact matched-filters matched to the “square” transmitterwaveform. The 16-bit output of the receiver gives us approximately 90 dB of dynamic range,before incoherent integration, when the receiver scaling is adjusted to give 2 bit RMS noise369