UM10139

Philips SemiconductorsVolume 1UM10139Chapter 2: Memory map2.3 Prefetch abort and data abort exceptionsThe LPC2141/2/4/6/8 generates the appropriate bus cycle abort exception if an access isattempted for an address that is in a reserved or unassigned address region. The regionsare:• Areas of the memory map that are not implemented for a specific ARM derivative. Forthe LPC2141/2/4/6/8, this is:– Address space between On-Chip Non-Volatile Memory and On-Chip SRAM,labelled "Reserved Address Space" in Figure 2. For 32 kB Flash device this ismemory address range from 0x0000 8000 to 0x3FFF FFFF, for 64 kB Flash devicethis is memory address range from 0x0001 0000 to 0x3FFF FFFF, for 128 kB Flashdevice this is memory address range from 0x0002 0000 to 0x3FFF FFFF, for256 kB Flash device this is memory address range from 0x0004 0000 to0x3FFF FFFF while for 512 kB Flash device this range is from 0x0008 0000 to0x3FFF FFFF.– Address space between On-Chip Static RAM and the Boot Block. Labelled"Reserved Address Space" in Figure 2. For 8 kB SRAM device this is memoryaddress range from 0x4000 2000 to 0x7FFF CFFF, for 16 kB SRAM device this ismemory address range from 0x4000 4000 to 0x7FFF CFFF. For 32 kB SRAMdevice this range is from 0x4000 8000 to 0x7FCF FFFF where the 8 kB USB DMARAM starts, and from 0x7FD0 2000 to 0x7FFF CFFF.– Address space between 0x8000 0000 and 0xDFFF FFFF, labelled "ReservedAdress Space".– Reserved regions of the AHB and VPB spaces. See Figure 3.• Unassigned AHB peripheral spaces. See Figure 4.• Unassigned VPB peripheral spaces. See Table 2.For these areas, both attempted data access and instruction fetch generate an exception.In addition, a Prefetch Abort exception is generated for any instruction fetch that maps toan AHB or VPB peripheral address.Within the address space of an existing VPB peripheral, a data abort exception is notgenerated in response to an access to an undefined address. Address decoding withineach peripheral is limited to that needed to distinguish defined registers within theperipheral itself. For example, an access to address 0xE000 D000 (an undefined addresswithin the UART0 space) may result in an access to the register defined at address0xE000 C000. Details of such address aliasing within a peripheral space are not definedin the LPC2141/2/4/6/8 documentation and are not a supported feature.Note that the ARM core stores the Prefetch Abort flag along with the associatedinstruction (which will be meaningless) in the pipeline and processes the abort only if anattempt is made to execute the instruction fetched from the illegal address. This preventsaccidental aborts that could be caused by prefetches that occur when code is executedvery near a memory boundary.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 15