UM10139

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Philips SemiconductorsVolume 1<strong>UM10139</strong>Chapter 5: VICdo and how to process the interrupt request. However, it is recommended that only oneinterrupt source should be classified as FIQ. Classifying more than one interrupt sourcesas FIQ will increase the interrupt latency.Following the completion of the desired interrupt service routine, clearing of the interruptflag on the peripheral level will propagate to corresponding bits in VIC registers(VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can beserviced, it is necessary that write is performed into the VICVectAddr register before thereturn from interrupt is executed. This write will clear the respective interrupt flag in theinternal interrupt priority hardware.In order to disable the interrupt at the VIC you need to clear corresponding bit in theVICIntEnClr register, which in turn clears the related bit in the VICIntEnable register. Thisalso applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear therespective bits in VICSoftInt. For example, if VICSoftInt = 0x0000 0005 and bit 0 has to becleared, VICSoftIntClear = 0x0000 0001 will accomplish this. Before the new clearoperation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed inthe future, VICSoftIntClear = 0x0000 0000 must be assigned. Therefore writing 1 to anybit in Clear register will have one-time-effect in the destination register.If the watchdog is enabled for interrupt on underflow or invalid feed sequence only thenthere is no way of clearing the interrupt. The only way you could perform return frominterrupt is by disabling the interrupt at the VIC (using VICIntEnClr).Example:Assuming that UART0 and SPI0 are generating interrupt requests that are classified asvectored IRQs (UART0 being on the higher level than SPI0), while UART1 and I 2 C aregenerating non-vectored IRQs, the following could be one possibility for VIC setup:VICIntSelect = 0x0000 0000 ; SPI0, I2C, UART1 and UART0 are IRQ =>; bit10, bit9, bit7 and bit6=0VICIntEnable = 0x0000 06C0 ; SPI0, I2C, UART1 and UART0 are enabled interrupts =>; bit10, bit9, bit 7 and bit6=1VICDefVectAddr = 0x...; holds address at what routine for servicing; non-vectored IRQs (i.e. UART1 and I2C) startsVICVectAddr0 = 0x...; holds address where UART0 IRQ service routine startsVICVectAddr1 = 0x...; holds address where SPI0 IRQ service routine startsVICVectCntl0 = 0x0000 0026 ; interrupt source with index 6 (UART0) is enabled as; the one with priority 0 (the highest)VICVectCntl1 = 0x0000 002A ; interrupt source with index 10 (SPI0) is enabled; as the one with priority 1After any of IRQ requests (SPI0, I 2 C, UART0 or UART1) is made, microcontroller willredirect code execution to the address specified at location 0x0000 0018. For vectoredand non-vectored IRQ’s the following instruction could be placed at 0x0000 0018:LDR pc, [pc,#-0xFF0]This instruction loads PC with the address that is present in VICVectAddr register.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 64
Philips SemiconductorsVolume 1<strong>UM10139</strong>Chapter 5: VICIn case UART0 request has been made, VICVectAddr will be identical to VICVectAddr0,while in case SPI0 request has been made value from VICVectAddr1 will be found here. Ifneither UART0 nor SPI0 have generated IRQ request but UART1 and/or I 2 C were thereason, content of VICVectAddr will be identical to VICDefVectAddr.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 65
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UM10139

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