UM10139

Philips SemiconductorsVolume 1UM10139Chapter 8: GPIOTable 75:RegisternameAside from the 32-bit long and word only accessible FIOMASK register, every fast GPIOport can also be controlled via several byte and half-word accessible registers listed inTable 75 and Table 76, too. Next to providing the same functions as the FIOMASKregister, these additional registers allow easier and faster access to the physical port pins.Fast GPIO port 0 Mask byte and half-word accessible register descriptionRegisterlength (bits)& accessAddress Description ResetvalueFIO0MASK0 8 (byte) 0x3FFF C010 Fast GPIO Port 0 Mask register 0. Bit 0 in FIO0MASK0 registercorresponds to P0.0 ... bit 7 to P0.7.FIO0MASK1 8 (byte) 0x3FFF C011 Fast GPIO Port 0 Mask register 1. Bit 0 in FIO0MASK1 registercorresponds to P0.8 ... bit 7 to P0.15.FIO0MASK2 8 (byte) 0x3FFF C012 Fast GPIO Port 0 Mask register 2. Bit 0 in FIO0MASK2 registercorresponds to P0.16 ... bit 7 to P0.23.FIO0MASK3 8 (byte) 0x3FFF C013 Fast GPIO Port 0 Mask register 3. Bit 0 in FIO0MASK3 registercorresponds to P0.24 ... bit 7 to P0.31.FIO0MASKL 16(half-word)FIO0MASKU 16(half-word)0x3FFF C0010x3FFF C012Fast GPIO Port 0 Mask Lower half-word register. Bit 0 inFIO0MASKL register corresponds to P0.0 ... bit 15 to P0.15.Fast GPIO Port 0 Mask Upper half-word register. Bit 0 inFIO0MASKU register corresponds to P0.16 ... bit 15 to P0.31.0x000x000x000x000x00000x0000Table 76:RegisternameFast GPIO port 1 Mask byte and half-word accessible register descriptionRegisterlength (bits)& accessAddress Description ResetvalueFIO1MASK0 8 (byte) 0x3FFF C010 Fast GPIO Port 1 Mask register 0. Bit 0 in FIO1MASK0 registercorresponds to P1.0 ... bit 7 to P1.7.FIO1MASK1 8 (byte) 0x3FFF C011 Fast GPIO Port 1 Mask register 1. Bit 0 in FIO1MASK1 registercorresponds to P1.8 ... bit 7 to P1.15.FIO1MASK2 8 (byte) 0x3FFF C012 Fast GPIO Port 1 Mask register 2. Bit 0 in FIO1MASK2 registercorresponds to P1.16 ... bit 7 to P1.23.FIO1MASK3 8 (byte) 0x3FFF C013 Fast GPIO Port 1 Mask register 3. Bit 0 in FIO1MASK3 registercorresponds to P1.24 ... bit 7 to P1.31.FIO1MASKL 16(half-word)FIO1MASKU 16(half-word)0x3FFF C0010x3FFF C012Fast GPIO Port 1 Mask Lower half-word register. Bit 0 inFIO1MASKL register corresponds to P1.0 ... bit 15 to P1.15.Fast GPIO Port 1 Mask Upper half-word register. Bit 0 inFIO1MASKU register corresponds to P1.16 ... bit 15 to P1.31.8.4.3 GPIO port Pin value register (IOPIN, Port 0: IO0PIN - 0xE002 8000 andPort 1: IO1PIN - 0xE002 8010; FIOPIN, Port 0: FIO0PIN - 0x3FFF C014and Port 1: FIO1PIN - 0x3FFF C034)This register provides the value of port pins that are configured to perform only digitalfunctions. The register will give the logic value of the pin regardless of whether the pin isconfigured for input or output, or as GPIO or an alternate digital function. As an example,a particular port pin may have GPIO input, GPIO output, UART receive, and PWM outputas selectable functions. Any configuration of that pin will allow its current logic state to beread from the IOPIN register.0x000x000x000x000x00000x0000© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 86