UM10139

Philips SemiconductorsVolume 1UM10139Chapter 13: SSP13.4.3 SSP Data Register (SSPDR - 0xE006 8008)Software can write data to be transmitted to this register, and read data that has beenreceived.Table 165: SSP Data Register (SSPDR - address 0xE006 8008) bit descriptionBit Symbol Description Reset value15:0 DATA Write: software can write data to be sent in a future frame to thisregister whenever the TNF bit in the Status register is 1,indicating that the Tx FIFO is not full. If the Tx FIFO waspreviously empty and the SSP controller is not busy on the bus,transmission of the data will begin immediately. Otherwise thedata written to this register will be sent as soon as all previousdata has been sent (and received). If the data length is less than16 bits, software must right-justify the data written to this register.0x0000Read: software can read data from this register whenever theRNE bit in the Status register is 1, indicating that the Rx FIFO isnot empty. When software reads this register, the SSP controllerreturns data from the least recent frame in the Rx FIFO. If thedata length is less than 16 bits, the data is right-justified in thisfield with higher order bits filled with 0s.13.4.4 SSP Status Register (SSPSR - 0xE006 800C)This read-only register reflects the current status of the SSP controller.Table 166: SSP Status Register (SSPDR - address 0xE006 800C) bit descriptionBit Symbol Description Reset value0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 10 if not.1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 12 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is 0empty, 1 if not.3 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if 0not.4 BSY Busy. This bit is 0 if the SSP controller is idle, or 1 if it is 0currently sending/receiving a frame and/or the Tx FIFO is notempty.7:5 - Reserved, user software should not write ones to reserved bits.The value read from a reserved bit is not defined.NA13.4.5 SSP Clock Prescale Register (SSPCPSR - 0xE006 8010)This register controls the factor by which the Prescaler divides the VPB clock PCLK toyield the prescaler clock that is, in turn, divided by the SCR factor in SSPCR0, todetermine the bit clock.Table 167: SSP Clock Prescale Register (SSPCPSR - address 0xE006 8010) bit descriptionBit Symbol Description Reset value7:0 CPSDVSR This even value between 2 and 254, by which PCLK is divided 0to yield the prescaler output clock. Bit 0 always reads as 0.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 191