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Philips SemiconductorsVolume 1UM10139Chapter 3: System Control Block3.10 Reset3.9.4 Power control usage notesAfter every reset, the PCONP register contains the value that enables all interfaces andperipherals controlled by the PCONP to be enabled. Therefore, apart from properconfiguring via peripheral dedicated registers, the user’s application has no need toaccess the PCONP in order to start using any of the on-board peripherals.Power saving oriented systems should have 1s in the PCONP register only in positionsthat match peripherals really used in the application. All other bits, declared to be"Reserved" or dedicated to the peripherals not used in the current application, must becleared to 0.Reset has two sources on the LPC2141/2/4/6/8: the RESET pin and Watchdog Reset.The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion ofchip Reset by any source starts the Wakeup Timer (see description in Section 3.12“Wakeup timer” in this chapter), causing reset to remain asserted until the external Resetis de-asserted, the oscillator is running, a fixed number of clocks have passed, and theon-chip circuitry has completed its initialization. The relationship between Reset, theoscillator, and the Wakeup Timer are shown in Figure 10.The Reset glitch filter allows the processor to ignore external reset pulses that are veryshort, and also determines the minimum duration of RESET that must be asserted inorder to guarantee a chip reset. Once asserted, RESET pin can be deasserted only whencrystal oscillator is fully running and an adequate signal is present on the X1 pin of themicrocontroller. Assuming that an external crystal is used in the crystal oscillatorsubsystem, after power on, the RESET pin should be asserted for 10 ms. For allsubsequent resets when crystal oscillator is already running and stable signal is on the X1pin, the RESET pin needs to be asserted for 300 ns only.When the internal Reset is removed, the processor begins executing at address 0, whichis initially the Reset vector mapped from the Boot Block. At that point, all of the processorand peripheral registers have been initialized to predetermined values.External and internal Resets have some small differences. An external Reset causes thevalue of certain pins to be latched to configure the part. External circuitry cannotdetermine when an internal Reset occurs in order to allow setting up those special pins,so those latches are not reloaded during an internal Reset. Pins that are examined duringan external Reset for various purposes are: P1.20/TRACESYNC, P1.26/RTCK (seechapters "Pin Configuration" on page 66 and "Pin Connect Block" on page 75). Pin P0.14(see "Flash Memory System and Programming" chapter on page 291) is examined byon-chip bootloader when this code is executed after every Reset.It is possible for a chip Reset to occur during a Flash programming or erase operation.The Flash memory will interrupt the ongoing operation and hold off the completion ofReset to the CPU until internal Flash high voltages have settled.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 38