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Philips SemiconductorsVolume 1<strong>UM10139</strong>Chapter 15: TIMER0 and TIMER115.5.8 Match Control Register (MCR, TIMER0: T0MCR - 0xE000 4014 andTIMER1: T1MCR - 0xE000 8014)The Match Control Register is used to control what operations are performed when one ofthe Match Registers matches the Timer Counter. The function of each of the bits is shownin Table 241.Table 241: Match Control Register (MCR, TIMER0: T0MCR - address 0xE000 4014 and TIMER1: T1MCR - address0xE000 8014) bit descriptionBit Symbol Value Description Resetvalue0 MR0I 1 Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 00 This interrupt is disabled1 MR0R 1 Reset on MR0: the TC will be reset if MR0 matches it. 00 Feature disabled.2 MR0S 1 Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0the TC.0 Feature disabled.3 MR1I 1 Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 00 This interrupt is disabled4 MR1R 1 Reset on MR1: the TC will be reset if MR1 matches it. 00 Feature disabled.5 MR1S 1 Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0the TC.0 Feature disabled.6 MR2I 1 Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 00 This interrupt is disabled7 MR2R 1 Reset on MR2: the TC will be reset if MR2 matches it. 00 Feature disabled.8 MR2S 1 Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0the TC.0 Feature disabled.9 MR3I 1 Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 00 This interrupt is disabled10 MR3R 1 Reset on MR3: the TC will be reset if MR3 matches it. 00 Feature disabled.11 MR3S 1 Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0the TC.0 Feature disabled.15:12 - Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.NA© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 248
Philips SemiconductorsVolume 1<strong>UM10139</strong>Chapter 15: TIMER0 and TIMER115.5.9 Capture Registers (CR0 - CR3)Each Capture register is associated with a device pin and may be loaded with the TimerCounter value when a specified event occurs on that pin. The settings in the CaptureControl Register register determine whether the capture function is enabled, and whethera capture event happens on the rising edge of the associated pin, the falling edge, or onboth edges.15.5.10 Capture Control Register (CCR, TIMER0: T0CCR - 0xE000 4028 andTIMER1: T1CCR - 0xE000 8028)The Capture Control Register is used to control whether one of the four Capture Registersis loaded with the value in the Timer Counter when the capture event occurs, and whetheran interrupt is generated by the capture event. Setting both the rising and falling bits at thesame time is a valid configuration, resulting in a capture event for both edges. In thedescription below, "n" represents the Timer number, 0 or 1.Table 242: Capture Control Register (CCR, TIMER0: T0CCR - address 0xE000 4028 and TIMER1: T1CCR - address0xE000 8028) bit descriptionBit Symbol Value Description Resetvalue0 CAP0RE 1 Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to 0be loaded with the contents of TC.0 This feature is disabled.1 CAP0FE 1 Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to 0be loaded with the contents of TC.0 This feature is disabled.2 CAP0I 1 Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt. 00 This feature is disabled.3 CAP1RE 1 Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to 0be loaded with the contents of TC.0 This feature is disabled.4 CAP1FE 1 Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to 0be loaded with the contents of TC.0 This feature is disabled.5 CAP1I 1 Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt. 00 This feature is disabled.6 CAP2RE 1 Capture on CAPn.2 rising edge: A sequence of 0 then 1 on CAPn.2 will cause CR2 to 0be loaded with the contents of TC.0 This feature is disabled.7 CAP2FE 1 Capture on CAPn.2 falling edge: a sequence of 1 then 0 on CAPn.2 will cause CR2 to 0be loaded with the contents of TC.0 This feature is disabled.8 CAP2I 1 Interrupt on CAPn.2 event: a CR2 load due to a CAPn.2 event will generate an interrupt. 00 This feature is disabled.9 CAP3RE 1 Capture on CAPn.3 rising edge: a sequence of 0 then 1 on CAPn.3 will cause CR3 to 0be loaded with the contents of TC.0 This feature is disabled.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 249
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