UM10139

Philips SemiconductorsVolume 1UM10139Chapter 4: MAM Modulethe Prefetch and Branch Trail Buffer is taken, a stall of several clocks is needed to load theBranch Trail Buffer. Subsequently, there will typically be no further instructionfetch delaysuntil a new and different branch occurs.4.3 MAM blocksThe Memory Accelerator Module is divided into several functional blocks:• A Flash Address Latch and an incrementor function to form prefetch addresses• A 128-bit Prefetch Buffer and an associated Address latch and comparator• A 128-bit Branch Trail Buffer and an associated Address latch and comparator• A 128-bit Data Buffer and an associated Address latch and comparator• Control logic• Wait logicFigure 12 shows a simplified block diagram of the Memory Accelerator Module data paths.In the following descriptions, the term “fetch” applies to an explicit Flash read request fromthe ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the currentprocessor fetch address.4.3.1 Flash memory bankThere is one bank of Flash memory with the LPC2141/2/4/6/8 MAM.Flash programming operations are not controlled by the MAM, but are handled as aseparate function. A “boot block” sector contains Flash programming algorithms that maybe called as part of the application program, and a loader that may be run to allow serialprogramming of the Flash memory.Memory AddressFlash MemoryBankARM Local BusBUSINTERFACEBUFFERSMemory DataFig 12. Simplified block diagram of the Memory Accelerator Module (MAM)© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 45