UM10139

Philips SemiconductorsVolume 1UM10139Chapter 14: USB Device ControllerTable 175: USB Interrupt Status register (USBIntSt - address 0xE01F C1C0) bit descriptionBit Symbol Description Resetvalue8 USB_need_clock USB need clock indicator. This bit is set to 1 when a USB0activity/change of state on the USB data pins is detected, and itindicates that a USB PLL supplied clock of 48 MHz is needed. Once theUSB_need_clock becomes one, it resets to zero 3 ms after the lastframe has been received/sent. A change of this bit from 0 to 1 can wakeup the microcontroller if an activity on the USB bus is selected to wakeup the part from the Power-down mode (see Section 3.5.3 “InterruptWakeup register (INTWAKE - 0xE01F C144)” on page 22 for details).Also see Section 3.8.8 “PLL and Power-down mode” on page 32 andSection 3.9.2 “Power Control register (PCON - 0xE01F COCO)” onpage 35 for considerations about the USB PLL and invoking the PowerDown mode.30:9 - Reserved, user software should not write ones to reserved bits. The NAvalue read from a reserved bit is not defined.31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared the ORed output ofthe USB interrupt lines is not seen by the Vectored Interrupt Controller.114.7.2 USB Device Interrupt Status register (USBDevIntSt - 0xE009 0000)Interrupt status register holds the value of the interrupt. A 0 indicates no interrupt and 1indicates the presence of the interrupt. The USBDevIntSt is a read only register.Table 176: USB Device Interrupt Status register (USBDevIntSt - address 0xE009 0000) bit allocationReset value: 0x0000 0000Bit 31 30 29 28 27 26 25 24Symbol - - - - - - - -Bit 23 22 21 20 19 18 17 16Symbol - - - - - - - -Bit 15 14 13 12 11 10 9 8Symbol - - - - - - EPR_INT EP_RLZEDBit 7 6 5 4 3 2 1 0Symbol TxENDPKT Rx CDFULL CCEMTY DEV_STAT EP_SLOW EP_FAST FRAMEENDPKTTable 177: USB Device Interrupt Status register (USBDevIntSt - address 0xE009 0000) bit descriptionBit Symbol Description Reset value0 FRAME The frame interrupt occurs every 1 ms. This is to be used in isochronous packet 0transfer.1 EP_FAST This is the fast interrupt transfer for the endpoint. If an Endpoint Interrupt Priority 0register bit is set, the endpoint interrupt will be routed to this bit.2 EP_SLOW This is the Slow interrupt transfer for the endpoint. If an Endpoint Interrupt Priority 0Register bit is not set, the endpoint interrupt will be routed to this bit.3 DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs. 0Refer to Section 14.9.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” onpage 225.4 CCEMTY The command code register is empty (New command can be written). 15 CDFULL Command data register is full (Data can be read now). 09397 750 XXXXX © Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 201