UM10139

Philips SemiconductorsVolume 1UM10139Chapter 19: RTC19.4.1 RTC interruptsInterrupt generation is controlled through the Interrupt Location Register (ILR), CounterIncrement Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register(AMR). Interrupts are generated only by the transition into the interrupt state. The ILRseparately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of thetime counters. If CIIR is enabled for a particular counter, then every time the counter isincremented an interrupt is generated. The alarm registers allow the user to specify a dateand time for an interrupt to be generated. The AMR provides a mechanism to mask alarmcompares. If all nonmasked alarm registers match the value in their corresponding timecounter, then an interrupt is generated.The RTC interrupt can bring the microcontroller out of power-down mode if the RTC isoperating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is enabledfor wakeup and its selected event occurs, XTAL1/2 pins associated oscillator wakeupcycle is started. For details on the RTC based wakeup process see Section 3.5.3“Interrupt Wakeup register (INTWAKE - 0xE01F C144)” on page 22 and Section 3.12“Wakeup timer” on page 41.19.4.2 Miscellaneous register groupTable 264 summarizes the registers located from 0 to 7 of A[6:2]. More detaileddescriptions follow.Table 264: Miscellaneous registersName Size Description Access AddressILR 2 Interrupt Location. Reading this location R/W 0xE002 4000indicates the source of an interrupt. Writing aone to the appropriate bit at this location clearsthe associated interrupt.CTC 15 Clock Tick Counter. Value from the clock RO 0xE002 4004divider.CCR 4 Clock Control Register. Controls the function of R/W 0xE002 4008the clock divider.CIIR 8 Counter Increment Interrupt. Selects which R/W0xE002 400Ccounters will generate an interrupt when theyare incremented.AMR 8 Alarm Mask Register. Controls which of the R/W 0xE002 4010alarm registers are masked.CTIME0 32 Consolidated Time Register 0 RO 0xE002 4014CTIME1 32 Consolidated Time Register 1 RO 0xE002 4018CTIME2 32 Consolidated Time Register 2 RO 0xE002 401C19.4.3 Interrupt Location Register (ILR - 0xE002 4000)The Interrupt Location Register is a 2-bit register that specifies which blocks aregenerating an interrupt (see Table 265). Writing a one to the appropriate bit clears thecorresponding interrupt. Writing a zero has no effect. This allows the programmer to readthis register and write back the same value to clear only the interrupt that is detected bythe read.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 277