UM10139

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Philips SemiconductorsVolume 1<strong>UM10139</strong>Chapter 8: GPIOstr r2,[r1]str r2,[r0]str r2,[r1]/*Generate 2 pulses on the slow port*/str r5,[r3]str r5,[r4]str r5,[r3]str r5,[r4]loop: b loopFigure 17 illustrates the code from above executed from the LPC2148 Flash memory. ThePLL generated F CCLK =60 MHz out of external F OSC = 12 MHz. The MAM was fullyenabled with MEMCR = 2 and MEMTIM = 3, and VPBDIV = 1 (PCLK = CCLK).Fig 17. Illustration of the fast and slow GPIO access and output showing 3.5 x increase of the pin outputfrequency© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 94
<strong>UM10139</strong>Chapter 9: Universal Asynchronous Receiver/Transmitter 0(UART0)Rev. 01 — 15 August 2005User manual9.1 Features9.2 Pin description• 16 byte Receive and Transmit FIFOs• Register locations conform to ‘550 industry standard.• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.• Built-in fractional baud rate generator with autobauding capabilities.• Mechanism that enables software and hardware flow control implementation.Table 95: UART0 pin descriptionPin Type DescriptionRXD0 Input Serial Input. Serial receive data.TXD0 Output Serial Output. Serial transmit data.9.3 Register descriptionUART0 contains registers organized as shown in Table 96. The Divisor Latch Access Bit(DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 95
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UM10139Chapter 23: Embedded Trace M
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UM10139

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