UM10139

Philips SemiconductorsVolume 1UM10139Chapter 25: Supplementary information0xE001 4000) bit description . . . . . . . . . . . . .259Table 249:PWM Timer Control Register (PWMTCR -address 0xE001 4004) bit description . . . . . .260Table 250:Match Control Register (MCR, TIMER0: T0MCR -address 0xE000 4014 and TIMER1: T1MCR -address 0xE000 8014) bit description . . . . . .261Table 251:PWM Control Register (PWMPCR - address0xE001 404C) bit description . . . . . . . . . . . . .262Table 252:PWM Latch Enable Register (PWMLER - address0xE001 4050) bit description . . . . . . . . . . . . .264Table 253:ADC pin description . . . . . . . . . . . . . . . . . . . .265Table 254:ADC registers . . . . . . . . . . . . . . . . . . . . . . . . .266Table 255:A/D Control Register (AD0CR - address0xE003 4000 and AD1CR - address0xE006 0000) bit description . . . . . . . . . . . . .267Table 256:A/D Global Data Register (AD0GDR - address0xE003 4004 and AD1GDR - address0xE006 0004) bit description . . . . . . . . . . . . .268Table 257:A/D Global Start Register (ADGSR - address0xE003 4008) bit description . . . . . . . . . . . . .269Table 258:A/D Status Register (ADSTAT, ADC0: AD0STAT -address 0xE003 4004 and ADC1: AD1STAT -address 0xE006 0004) bit description . . . . . .270Table 259:A/D Status Register (ADSTAT, ADC0: AD0STAT -address 0xE003 4004 and ADC1: AD1STAT -address 0xE006 0004) bit description . . . . . .270Table 260:A/D Data Registers (ADDR0 to ADDR7, ADC0:AD0DR0 to AD0DR7 - 0xE003 4010 to 0xE003402C and ADC1: AD1DR0 to AD1DR7- 0xE0060010 to 0xE006 402C) bit description . . . . . .271Table 261:DAC pin description . . . . . . . . . . . . . . . . . . . .273Table 262:DAC Register (DACR - address 0xE006 C000) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .273Table 263:Real Time Clock (RTC) register map . . . . . . .276Table 264:Miscellaneous registers . . . . . . . . . . . . . . . . .277Table 265:Interrupt Location Register (ILR - address0xE002 4000) bit description . . . . . . . . . . . . .278Table 266:Clock Tick Counter Register (CTCR - address0xE002 4004) bit description . . . . . . . . . . . . .278Table 267:Clock Control Register (CCR - address0xE002 4008) bit description . . . . . . . . . . . . .278Table 268:Counter Increment Interrupt Register (CIIR -address 0xE002 400C) bit description . . . . . .279Table 269:Alarm Mask Register (AMR - address0xE002 4010) bit description . . . . . . . . . . . . .279Table 270:Consolidated Time register 0 (CTIME0 - address0xE002 4014) bit description . . . . . . . . . . . . .280Table 271:Consolidated Time register 1 (CTIME1 - address0xE002 4018) bit description . . . . . . . . . . . . .280Table 272:Consolidated Time register 2 (CTIME2 - address0xE002 401C) bit description . . . . . . . . . . . . .280Table 273:Time counter relationships and values. . . . . . 281Table 274:Time counter registers . . . . . . . . . . . . . . . . . . 281Table 275:Alarm registers. . . . . . . . . . . . . . . . . . . . . . . . 282Table 276:Reference clock divider registers . . . . . . . . . . 283Table 277:Prescaler Integer register (PREINT - address0xE002 4080) bit description . . . . . . . . . . . . . 283Table 278:Prescaler Integer register (PREFRAC - address0xE002 4084) bit description . . . . . . . . . . . . . 283Table 279:Prescaler cases where the Integer Counter reloadvalue is incremented . . . . . . . . . . . . . . . . . . . 285Table 280:Recommended values for the RTC external32 kHz oscillator C X1/X2 components . . . . . . . 286Table 281:Watchdog register map . . . . . . . . . . . . . . . . . 288Table 282:Watchdog operating modes selection . . . . . . 288Table 283:Watchdog Mode register (WDMOD - address0xE000 0000) bit description . . . . . . . . . . . . . 289Table 284:Watchdog Timer Constant register (WDTC -address 0xE000 0004) bit description . . . . . . 289Table 285:Watchdog Feed register (WDFEED - address0xE000 0008) bit description . . . . . . . . . . . . . 289Table 286:Watchdog Timer Value register (WDTV - address0xE000 000C) bit description. . . . . . . . . . . . . 289Table 287:Flash sectors in LPC2141, LPC2142, LPC2144,LPC2146 and LPC2148 . . . . . . . . . . . . . . . . . 296Table 288:ISP command summary. . . . . . . . . . . . . . . . . 298Table 289:ISP Unlock command. . . . . . . . . . . . . . . . . . . 298Table 290:ISP Set Baud Rate command . . . . . . . . . . . . 298Table 291:Correlation between possible ISP baudrates andexternal crystal frequency (in MHz) . . . . . . . . 299Table 292:ISP Echo command . . . . . . . . . . . . . . . . . . . . 299Table 293:ISP Write to RAM command . . . . . . . . . . . . . 300Table 294:ISP Read memory command. . . . . . . . . . . . . 300Table 295:ISP Prepare sector(s) for write operationcommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301Table 296:ISP Copy command . . . . . . . . . . . . . . . . . . . . 301Table 297:ISP Go command. . . . . . . . . . . . . . . . . . . . . . 302Table 298:ISP Erase sector command . . . . . . . . . . . . . . 302Table 299:ISP Blank check sector command . . . . . . . . . 303Table 300:ISP Read Part Identification numbercommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Table 301:LPC214x Part Identification numbers . . . . . . 303Table 302:ISP Read Boot code version numbercommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Table 303:ISP Compare command. . . . . . . . . . . . . . . . . 304Table 304:ISP Return codes Summary . . . . . . . . . . . . . 304Table 305:IAP Command Summary . . . . . . . . . . . . . . . . 306Table 306:IAP Prepare sector(s) for write operationcommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307Table 307:IAP Copy RAM to Flash command . . . . . . . . 308Table 308:IAP Erase sector(s) command . . . . . . . . . . . . 308Table 309:IAP Blank check sector(s) command . . . . . . . 309continued >>© Koninklijke Philips Electronics N.V. 2005. All rights reserved.User manual Rev. 01 — 15 August 2005 336