Efficient Rendering with DirectX 12 on Intel Graphics

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GPU Memory Residency in WDDM 2.0 Directly exposes control over physical residency – Memory referenced by the GPU must be made “resident” No dedicated video memory on Intel processors – “Resident” resources are allocated out of DRAM OS uses up to 45% of DRAM for graphics applications – Ex. 1.8GB on a 4GB system, 3.6GB on an 8GB system, … – Global limit across the system, not per-process – Rest is reserved for regular CPU/OS use Copyright © 2015, Intel Corporation. All rights reserv ed. *Other names and brands may be claimed as the property of others. 26
Memory Residency Best Practices Allocations are initially made resident – Resource creation will fail if residency budget is exceeded OS will request that background apps trim residency – Misbehaved applications will be suspended from rendering – i.e. their GPU work will not be scheduled/make progress Be a good citizen; provide a good user experience – Handle allocation failures and trim requests gracefully – Evict idle resources, trim streaming pools, remove detailed mips, drop quality settings, etc. Copyright © 2015, Intel Corporation. All rights reserv ed. *Other names and brands may be claimed as the property of others. 27
Page 1 and 2: Efficient
Page 3 and 4: Decoder Cheat-sheet Intel 4 th Gen
Page 5 and 6: Graphics APIs and Overhead Most GP
Page 7 and 8: Thinner Intel Graphics Driver To a
Page 9 and 10: DirectX 12
Page 11 and 12: Commands and State Copyright © 201
Page 13 and 14: Commands in DirectX</strong
Page 15 and 16: DirectX 11 Deferre
Page 17 and 18: Commands in DirectX</strong
Page 19 and 20: Pipeline State Objects Create PSOs
Page 21 and 22: DirectX 12
Page 23 and 24: Multi-engine on Haswell/Broadwell
Page 25: GPU Memory in WDDM 1.x Previous AP
Page 29 and 30: Typical Discrete GPU Memory Applica
Page 31 and 32: Haswell GPU Virtual Address Limit
Page 33 and 34: Resource Binding Copyright © 2015,
Page 35 and 36: Resource Descriptors Not an API ob
Page 37 and 38: Root Signature Think of it like a
Page 39 and 40: Root Constants Pass a small number
Page 41 and 42: Descriptor Tables Maps continuous
Page 43 and 44: Root Signature Example Root Signatu
Page 45 and 46: Root Signature Example (HLSL) Root
Page 47 and 48: Binding Example Root Signature 0 De
Page 49 and 50: Haswell/Broadwell Resource Binding
Page 51 and 52: Haswell/Broadwell Descriptor Tables
Page 53 and 54: Haswell/Broadwell Descriptor Tables
Page 55 and 56: Resource Binding Summary Minimize
Page 57 and 58: Summary Copyright © 2015, Intel Co
Page 59: Questions? Follow @DirectX

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