Efficient Rendering with DirectX 12 on Intel Graphics

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Root Signature Example Root Signature 0 Descriptor Table t1 b1 t4 t5 1 Descriptor Table u0 b2 D3D<strong>12</strong>_DESCRIPTOR_RANGE Param0Ranges[3]; Param0Ranges[0].Init(D3D<strong>12</strong>_DESCRIPTOR_RANGE_SRV, 1, 1); // t1 Param0Ranges[1].Init(D3D<strong>12</strong>_DESCRIPTOR_RANGE_CBV, 1, 1); // b1 Param0Ranges[2].Init(D3D<strong>12</strong>_DESCRIPTOR_RANGE_SRV, 2, 4); // t4-t5 D3D<strong>12</strong>_DESCRIPTOR_RANGE Param1Ranges[2]; Param1Ranges[0].Init(D3D<strong>12</strong>_DESCRIPTOR_RANGE_UAV, 1, 0); // u0 Param1Ranges[1].Init(D3D<strong>12</strong>_DESCRIPTOR_RANGE_CBV, 1, 2); // b2 // Visibility to all stages allows sharing binding tables D3D<strong>12</strong>_ROOT_PARAMETER Param[2]; Param[0].InitAsDescriptorTable(3, Param0Ranges, D3D<strong>12</strong>_SHADER_VISIBILITY_ALL); Param[1].InitAsDescriptorTable(2, Param1Ranges, D3D<strong>12</strong>_SHADER_VISIBILITY_ALL); Copyright © 2015, Intel Corporation. All rights reserv ed. *Other names and brands may be claimed as the property of others. 42
Root Signature Example Root Signature 0 Descriptor Table t1 b1 t4 t5 1 Descriptor Table 2 Shader Resource View u0 t0 b2 3 uint4 Constant b0 ... Param[2].InitAsShaderResourceView(1, 0); // t0 Param[3].InitAsConstants(4, 0); // b0 (4x32-bit constants) Copyright © 2015, Intel Corporation. All rights reserv ed. *Other names and brands may be claimed as the property of others. 43
Page 1 and 2: Efficient
Page 3 and 4: Decoder Cheat-sheet Intel 4 th Gen
Page 5 and 6: Graphics APIs and Overhead Most GP
Page 7 and 8: Thinner Intel Graphics Driver To a
Page 9 and 10: DirectX 12
Page 11 and 12: Commands and State Copyright © 201
Page 13 and 14: Commands in DirectX</strong
Page 15 and 16: DirectX 11 Deferre
Page 17 and 18: Commands in DirectX</strong
Page 19 and 20: Pipeline State Objects Create PSOs
Page 21 and 22: DirectX 12
Page 23 and 24: Multi-engine on Haswell/Broadwell
Page 25 and 26: GPU Memory in WDDM 1.x Previous AP
Page 27 and 28: Memory Residency Best Practices Al
Page 29 and 30: Typical Discrete GPU Memory Applica
Page 31 and 32: Haswell GPU Virtual Address Limit
Page 33 and 34: Resource Binding Copyright © 2015,
Page 35 and 36: Resource Descriptors Not an API ob
Page 37 and 38: Root Signature Think of it like a
Page 39 and 40: Root Constants Pass a small number
Page 41: Descriptor Tables Maps continuous
Page 45 and 46: Root Signature Example (HLSL) Root
Page 47 and 48: Binding Example Root Signature 0 De
Page 49 and 50: Haswell/Broadwell Resource Binding
Page 51 and 52: Haswell/Broadwell Descriptor Tables
Page 53 and 54: Haswell/Broadwell Descriptor Tables
Page 55 and 56: Resource Binding Summary Minimize
Page 57 and 58: Summary Copyright © 2015, Intel Co
Page 59: Questions? Follow @DirectX

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