Qualification of the Assembly Process of Flip-Chip BGA Packages ...
Qualification of the Assembly Process of Flip-Chip BGA Packages ...
Qualification of the Assembly Process of Flip-Chip BGA Packages ...
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2.1 What is <strong>Qualification</strong>? [7]<br />
Texas Tech University, Nivetha Shivan, May 2012<br />
CHAPTER 2<br />
PURPOSE OF THIS QUALIFICATION<br />
Whenever a product, process or package type is changed, it is required to validate that<br />
<strong>the</strong>se changes did not affect <strong>the</strong> functionality and reliability <strong>of</strong> <strong>the</strong> final product. The<br />
devices are subjected to a baseline <strong>of</strong> acceptance tests which are capable <strong>of</strong> stimulating<br />
device and packaging failures. These failures are stimulated in an accelerated manner as<br />
compared <strong>the</strong>ir normal use conditions. The motive behind any qualification project is to<br />
look for any new and unique failure modes, and also to look for any situations where <strong>the</strong><br />
stress tests will induce invalid failures.<br />
2.2 Quad Data Rate SRAM<br />
Memory devices are semiconductor units that are capable <strong>of</strong> retaining digital data.<br />
Depending on whe<strong>the</strong>r <strong>the</strong> memory loses its contents upon power removal, it is divided<br />
into volatile and non-volatile memory. Volatile being <strong>the</strong> type which loses and non-<br />
volatile being <strong>the</strong> one which does not lose its contents. The volatile memory is divided<br />
into static and dynamic.<br />
Unlike dynamic memory, static memory does not have to be refreshed periodically. It<br />
also runs faster than <strong>the</strong> former type <strong>of</strong> memories. There are two types <strong>of</strong> SRAMs –<br />
Synchronous and Asynchronous. The asynchronous SRAMs do not have a clock signal<br />
which can control when <strong>the</strong> data input and output signals are transferred. The data output<br />
comes out after a delay with <strong>the</strong> data input signal. But in synchronous SRAM, <strong>the</strong>re are<br />
clock signals which can control <strong>the</strong> timing <strong>of</strong> <strong>the</strong> data input and output signals because <strong>of</strong><br />
which <strong>the</strong> frequency with which <strong>the</strong> signals are transferred can be increased. Hence Sync<br />
SRAMs are faster than Async SRAMs.<br />
6