Qualification of the Assembly Process of Flip-Chip BGA Packages ...

Texas Tech University, Nivetha Shivan, May 2012
ACKNOWLEDGEMENTS
The inspiration for this project is based on my work during my internship period in
Cypress Semiconductor Corporation. Firstly, I would like to thank my manager
Mr. Sandeep Krishnegowda (Product Engineering Group Lead) and Cypress
Semiconductor‟s Memory Product Division (MPD) Sync SRAM group for giving me an
internship opportunity which proved very helpful in building my career.
I would like to thank my Thesis Advisor Dr. Richard Gale for his support during my
internship period and guidance in this work. I also want to thank Dr. Stephen Bayne who
has been a reason for my drive in his Electronic Design, Simulation and Testing course in
Spring 2011 which helped me to learn a lot.
I want to thank the team of engineers in Cypress – Mr. Mohammed Eslamy (Packaging
Engineering Manager), Mr. Cary Stubbles (Packaging Engineer Staff), Mr. Zhaomin Ji
(Reliability Engineer Principal) and Mr. Junwei Hu (Packaging Engineer Senior) for
helping me learn and making this project successful. I also want to thank Mrs. Judy
Tseng (Product Test Tech Specialist) for helping me learn the cross-section failure
analysis technique. I am grateful to Sonoscan industry for helping me in this project for
performing the acoustic microscopy technique. My thanks also goes to Mr. Cliff Neilson,
Tech Specialist who helped me with the stress test techniques. I also extend my thanks to
my colleagues in Cypress Semiconductors who have helped me to learn engineering in
the industry.
I want to thank all of my friends in Texas Tech University and Cypress Semiconductor
for being there for me throughout this endeavor. Last but not the least; I would like to
thank my parents in India for their love, trust and continuous support which instilled faith
in me for completing my Master‟s Thesis.
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