Qualification of the Assembly Process of Flip-Chip BGA Packages ...

More documents

Recommendations

Info

Texas Tech University, Nivetha Shivan, May 2012 plan listed in Table 3.3. It is necessary to subject these 4 TVs to the remaining stresses and correlate the decisions made from each step. It is only conclusive when a final decision is made based on the analysis of the results of the all of the stress tests. Lastly, TV3 also needs to pass the Engineering Qualification which uses the actual product die with higher speed. Engineering Qualification has a similar stress test plan as the Pre-engineering Qualification and also has essential read points. This way one variable is introduced at each Qualification step which will lead to a number of cycles of learning before we qualify the new interconnect technology for the new product. 63
Texas Tech University, Nivetha Shivan, May 2012 REFERENCES 1. M. Bundalo and P. Kasemir. Fundamentals of IC Assembly [Online]. Available: http://ecee.colorado.edu/~ecen5004/ECEN5004-Ch9.ppt 2. R. H. Katz. (1996). Lecture 5: Cost, Price, and Price for Performance [Online]. Available: http://bnrg.eecs.berkeley.edu/~randy/Courses/CS252.S96/Lecture05.pdf 3. Integrated Circuit Packaging [Online]. Available: http://en.wikipedia.org/wiki/Integrated_circuit_packaging 4. Tape Automated Bonding [Online]. Available: http://www.siliconfareast.com/tab.htm 5. J. H. Lau and S. R. Lee, “Solder-Bumped Flip Chip and Wire-Bonding Chip on CSP Substrate”, in Chip Scale Package Designs, Materials, Process, Reliability and Applications, New York, NY: McGraw-Hill, 1999, pp.3. 6. M. Ben-tzur and S. Daniel, “Die Edge Delamination – White paper”, unpublished. 7. Stress-Test-Driven Qualification of Integrated Circuits, JEDEC Standard JESD47G, 2009. 8. R. Y. Chen. Signal Integrity [Online]. Available: http://www.csee.umbc.edu/csee/research/vlsi/reports/si_chapter.pdf 9. Dr. K. Gilleo. The Chemistry & Physics of Underfill [Online]. Available: www.et-trends.com/files/NepWest98_Chem-UF.pdf 10. Lot Tolerance Percent Defective [Online]. Available: http://www.siliconfareast.com/ltpd_aql.htm 11. Engineering Statistics Handbook [Online]. Available: http://www.itl.nist.gov/div898/handbook/pmc/section2/pmc22.htm 12. Y. Wang and P. Hassell, “Measurement of Thermally Induced Warpage of BGA Packages/Substrates Using Phase-Stepping Shadow Moiré”, presented at the IEEWCPMT Electronic Packaging Technology Conference I, Atlanta, GA, 1997. 13. K. Creath and J. C. Wyant (1992). Optical Shop Testing, Moiré and Fringe Projection Techniques (2 nd ed.) [Online]. Available: http://www.optics.arizona.edu/jcwyant/optics513/chapternotes/chapter04/moirechapt ersecured.pdf 14. High Temperature Package Warpage Measurement Methodology, JEDEC Standard JESD22B112, 2005. 64
Page 1 and 2:
QUALIFICATION OF THE ASSEMBLY PROCE
Page 3 and 4:
Texas Tech University, Nivetha Shiv
Page 5 and 6:
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
1.3 Requirements of an IC Package [
Page 13 and 14:
1.5.2 Tape Automated Bonding [4] Te
Page 15 and 16:
2.1 What is Qualification? [7] Texa
Page 17 and 18:
Page 19 and 20:
Page 21 and 22: Texas Tech University, Nivetha Shiv
Page 23 and 24: 3.1.1.2 Underfill material [9] Texa
Page 41 and 42: 4.2.3 Pressure Cooker Technique [20
Page 45 and 46: 4.3.1.3 Leakage Test Texas Tech Uni
Page 59 and 60: Cleaning Texas Tech University, Niv
Page 61 and 62: 6.1 Results Texas Tech University,
Page 65 and 66: . Texas Tech University, Nivetha Sh
Page 67 and 68: 6.1.2 Pre-engineering Qualification
Page 71: Texas Tech University, Nivetha Shiv
show all

Qualification of the Assembly Process of Flip-Chip BGA Packages ...

Create successful ePaper yourself

Delete template?

Save as template?