Qualification of the Assembly Process of Flip-Chip BGA Packages ...

Texas Tech University, Nivetha Shivan, May 2012
Sync SRAMs are available in two types – Double Data Rate (DDR) and Quad Data Rate
(QDR). In both DDRs and QDRs, the read and write signals are transferred on both the
rising and falling edges of the clock. This increases the frequency with which the device
can be used. But in DDR, there is only one data bus which transfers the read and writes
data (common I/O), unlike in QDRs where there are two separate I/O buses for data
transfers. Hence in QDRs it is possible to transfer four words of data in one clock cycle,
unlike two in double data rate.
2.2.1 Existing QDR
QDR, QDR-II and QDR-II+ are the QDRs that are present in the market today for
networking and communication applications. These are available in speeds of 167MHz,
333MHz and 550MHz respectively. All of these QDRs used a 165 BGA package with the
traditional wire-bonding technology. Wire-bonded devices were examined for wire
fracture and package fracture failures under X-ray inspection.
2.2.2 Upcoming QDR
The upcoming next generation QDR has a more complex design than the current products
with high density memory cells. Owing to which, there are a large number of signals
coming from the die which needs special routing in order to bring out all the signals to
the package pins. The number of package signal pins in the new product is twice as much
as that of the earlier products. This product operates at a frequency much higher than the
previous products and the number of clocks present in this product is also more.
The die size of this product follows a much larger geometry than the previous QDRs
corresponding directly to the increased performance of this device and routing capability
during the design of the die. At the wafer fabrication level, an extra metal layer stack and
thicker Aluminium redistribution layer have been implemented in the upcoming QDR for
lower impedance in order to the meet the new product‟s requirements (high frequency).
7