mitac 8599.pdf - tim.id.au

8599 N/B Maintenance
the second display can only be realized through software engine.
Two separate buses, the 64 bit Host-to-GUI bus, and the 128 bit IGUI-to-Memory Controller bus are devised to ensure
concurrency of Host-to-GUI, and GUI-to-MC streaming. In the DDR-400 memory subsystem, the 128 bit IGUI-to-
MC bus attains 3.2 GB/s, around 52% wider bandwidth than the AGP 8X one. The DDR-400 unified memory
controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and the Memory Interface. The
Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP controller, Host Controller, and
the I/O bus masters based a default optimized priority list with the capability of dynamically prioritizing the I/O bus
master requests to offer a privileged service to 1) the isochronous downstream transfer to guarantee the min. latency,
& timely deliver, or 2) the PCI master downstream transfer to curb the latency within the max. tolerant period of 10us.
Prior to the memory access requests pushed into the M-data queue, any command complaint to the paging mechanism
is generated and pushed into the M-CMD queue. The M-data/M-CMD queue further orders and forwards these
queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling
the command requests in the background when the data request streamlines in the foreground.
Features :
PC2001 Compliance
High Performance Host Interface
- Supports Intel Pentium 4 processor family with data transfer rate
- Supports Hyper-Threading Technology
- Supports 12 outstanding transactions and out-of-order completion
- Supports Quasi-synchronous/asynchronous Host-to-DRAM timing
- Supports Master delivery System bus Interrupt
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