mitac 8599.pdf - tim.id.au

8599 N/B Maintenance
5.3 SiS963L(MuTIOL®Media I/O South Bridge) - 1
Host Bus Interface
Name Pin Attr Description
FERR# I
0.8V/2.65V -M
IGNNE# OD
0.8V/2.65V -M
NMI OD
0.8V/2.65V -M
INTR OD
0.8V/2.65V -M
APICD1 /
GPIOFF#
APICD0 /
THERM2#
I/OD
I
I/OD
I
0.8V/2.65V -M
CPUSLP# OD
0.8V/2.65V -M
STPCLK# OD
0.8V/2.65V -M
SMI# OD
0.8V/2.65V -M
INIT# OD
0.8V/2.65V -M
APICCK/
LDTREQ# /
AGPBUSY#
I
2.5V/3.3V -M
A20M# OD
0.8V/2.65V- M
Floating Point Error: CPU will assert this signal upon
a floating point error occurring.
Ignore Numeric Error: IGNNE# is asserted to inform
CPU to ignore a numeric error.
Non-Maskable Interrupt: A rising edge on NMI will
trigger a non-maskable interrupt to CPU.
Interrupt Request: High-level voltage of this signal
conveys to CPU that there is outstanding interrupt(s)
needed to be serviced.
APIC Data: APICD[1:0]
These two signals are used to send and receive APIC
data.
GPIO OFF: Turn off the system when input a low level
signal.
Thermal 2: Assert a SMI#/SCI# when input a low level
signal.
CPU Sleep: The CPUSLP# can be used to force CPU
enter the Sleep state.
Stop Clock: STPCLK# will be asserted to inhibit or
throttle CPU activities upon a pre-defined
power management event occurs.
System Management Interrupt: SMI# will be asserted
when a pre-defined power management event occurs.
Initialization: INIT is used to re-start the CPU without
flushing its internal caches and registers. In Pentium III
platform it is active high. This signal requires an external
pull-up resistor tied to VTT.
APIC Clock: This signal is used to determine when
valid data is being sent over the APCI bus.
LDTREQ# / AGPBUSY# (LDTREQ# for K8 use
only)
When a low active signal inputs, it will wake up system
from C3/S1.
Address 20 Mask: When A20M# is asserted, the CPU
A20 signal will be forced to “0”
MuTIOL 1G Connect Interface
Name Pin Attr Description
ZCLK I
3.3V - M
MuTIOL 1G I/O Connect Clock
ZUREQ I/O
1.8V - M
MuTIOL 1G I/O Conect Controll pins
ZDREQ I/O
1.8V - M
MuTIOL 1G I/O Conect Controll pins
ZSTB[1:0] I/O
1.8V - M
MuTIOL 1G I/O Connect Strobe
ZSTB[1:0]# I/O
1.8V - M
MuTIOL 1G Strobe Compliment
ZAD[16:0] I/O
1.8V - M
MuTIOL 1G Address/Data pins
ZVREF I -M MuTIOL 1G I/O reference voltage
ZCMP_N I -M MuTIOL 1G N-MOS Compensation Input
ZCMP_P I -M MuTIOL 1G P-MOS Compensation input
LPC Interface
Name Pin Attr Description
LAD[3:0] I/O
3.3V/5V-M
LDRQ# I
3.3V/5V-M
LDRQ1#
I
(GPIO1)
3.3V/5V-M
LFRAME# O
3.3V -M
SIRQ I/O
3.3V/5V -M
LPC Address/Data Bus:
LPC controller drives these four pins to transmit LPC
command, address, and data to LPC device.
LPC DMA Request 0:
This pin is used by LPC device to request DMA cycle.
LPC DMA Request 1:
This pin is used by LPC device to request DMA cycle.
LPC Frame:
This pin is used to notify LPC device that a start or a
abort LPC cycle will occur.
Serial IRQ:
This signal is used as the serial IRQ line signal.
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