mitac 8599.pdf - tim.id.au

8599 N/B Maintenance
5.2 SiS M661FX (IGUI Host Memory Controller) - 4
Digital Video Link Interface
Ball Name Ball Attr Description
VBCLK I
1.8V - M
VBHCLK O
1.8V - M
VBCAD I/O
1.8V - M
VBCTL[1:0] O
1.8V -M
VGPIO[3:2] I/O
1.8V - M
VBHSYNC I/O
1.8V - M
VBVSYNC I/O
1.8V - M
VBDE I/O
1.8V - M
VBGCLK I/O
1.8V - M
VBGCLK# I/O
1.8V - M
VBD[11:0] I/O
1.8V - M
VAHSYNC I/O
1.8V - M
VAVSYNC I/O
1.8V - M
VADE I/O
1.8V - M
VAGCLK I/O
1.8V - M
VAGCLK# I/O
1.8V - M
VAD[11:0] I/O
1.8V - M
Channel B/A Clock Input
VBCLK multiplexed with SBA0
VB Programming Interface Clock
VBHCLK multiplexed with RBF#
VB Programming Interface Data
VBCAD multiplexed with AREQ#
VB Data Control
VBCTL[1:0] multiplexed with AAD[29:28]
VB GPIO pins
VGPIO[3:2] multiplexed with IPE#/WBF#
Channel B H-Sync
VBHSYNC multiplexed with AAD30
Channel B V-Sync
VBVSYNC multiplexed with AAD31
Channel B Data Valid
VBDE multiplexed with AAD27
Channel B Clock Output.
This clock is used to trigger dual edge data
transfer. Perfect duty cycle is required.
VBGCLK multiplexed with AD_STB1
Channel B Differential Clock Output. (To support
Chrontel).
VBGCLK# multiplexed with AD_STB1#
Channel B Data
VBD[11:0] multiplexed with AAD
Channel A H-Sync
VAHSYNC multiplexed with AAD18
Channel A V-Sync
VAVSYNC multiplexed with AAD17
Channel A Data Valid
VADE multiplexed with AAD16
Channel A Clock Output.
This clock is used to trigger dual edge data 1.8V –
M transfer. Perfect duty cycle is required.
VAGCLK multiplexed with AD_STB0
Channel A Differential Clock Output. (To support
Chrontel).
VAGCLK# multiplexed with AD_STB0#
Channel A Data
VAD[11:0] multiplexed with AAD
Test Mode / Hardware Trap / Power Management
Ball Name Ball Attr Description
DLLEN# I/O
3.3V/5V– M
TRAP2 I
3.3V/5V– AUX
TRAP[1:0] I
3.3V/5V– M
ENTEST I
3.3V/5V– M
TESTMODE[2:0] I
3.3V/5V– M
AUXOK I
3.3V – AUXI
PCIRST# I
3.3V – AUXI
PWROK I
3.3V – AUXI
Hardware Trap pin (refer to section 5)
Hardware Trap pin (refer to section 5)
Hardware Trap pins (refer to section 5)
Test Mode enable pin
Test Mode select pin
Nand Tree Test: 100
Auxiliary Power OK :
This signal is supplied from the power source of
resume well. It is also used to reset the logic in
resume power well. If there is no auxiliary power
source on the system, this pin should be tied
together
with PWROK.
PCI Bus Reset :
PCIRST# is supplied from SiS963 MuTIOL ? ?1G
Media IO.
Main Power OK :
A high-level input to this signal indicates the
power being supplied to the system is in stable
operating state. During the period of PWROK
being low, CPURST and PCIRST# will all be
asserted until after PWROK goes high for 24 ms.
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