mitac 8599.pdf - tim.id.au

8599 N/B Maintenance
5.2 SiS M661FX (IGUI Host Memory Controller) - 1
Host Bus Interface
Ball Name Ball Attr Description
CPUCLK
I
CPUCLK#
0.71V – M
CPURST# O
0.9~1.8V – M
CPUPWRGD O
0.9~1.8V – M
ADS# I/O
0.9~1.8V – M
HASTB[1:0]# I/O
0.9~1.8V – M
HREQ[4:0]# I/O
0.9~1.8V – M
HA[31:3]# I/O
0.9~1.8V – M
BREQ0# O
0.9~1.8V – M
BPRI# O
0.9~1.8V – M
BNR# I/O
0.9~1.8V – M
HLOCK# I
0.9~1.8V – M
HIT# I/O
0.9~1.8V – M
Host differential clock input.
Host Bus Reset:
CPURST# is used to keep all the bus agents in the
same initial state before valid cycles issued.
CPUPWRGD is used to inform CPU that main
power is stable
Address Strobe :
Address Strobe is driven by CPU or SiSM661FX
to indicate the start of a CPU bus cycle.
Source synchronous address strobe used to latch
HREQ[4:0]# & HA[31:3]# at both falling and
rising edge.
HREQ[4:0]# & HA[16:3]# are latched by
HASTB0# HA[31:17]# are latched by HASTB1#
Request Command:
HREQ[4:0]# are used to define each transaction
type during the clock when ADS# is asserted and
the clock after ADS# is asserted.
Host Address Bus
Symmetric Agent Bus Request:
BREQ0# is driven by the symmetric agent to
request for the bus.
Priority Agent Bus Request:
BPRI# is driven by the priority agent that wants to
request the bus.
BPRI# has higher priority than BREQ0# to access
a bus.
Block Next Request:
This signal can be driven asserted by any bus agent
to block further requests being pipelined.
Host Lock :
CPU asserts HLOCK# to indicate the current bus
cycle is locked.
Keeping a Non-Modified Cache Line
Host Bus Interface (Continued)
Ball Name Ball Attr Description
HITM# I/O
0.9~1.8V – M
DEFER# O
0.9~1.8V – M
RS[2:0]# O
0.9~1.8V – M
HTRDY# O
0.9~1.8V – M
DRDY# I/O
0.9~1.8V – M
DBSY# I/O
0.9~1.8V – M
HD[63:0]# I/O
0.9~1.8V – M
DBI[3:0]# I/O
0.9~1.8V – M
Hits a Modified Cache Line:
Hit Modified indicates the snoop cycle hits a
modified line in the L1/L2 cache of CPU.
Defer Transaction Completion:
SiSM661FX will use this signal to indicate a retry
or defer response to host bus.
Response Status:
RS[2:0]# are driven by the response agent to
indicate the transaction response type. The
following shows the response type.
RS[2:0]# Response
000 Idle State
001 Retry
010 Defer
011 Reserved
100 Reserved
101 No data
110 Implicit Write-back
111 Normal
Target Ready:
During write cycles, response agent will drive
TRDY# to indicate it is ready to accept data.
Data Ready:
DRDY# is driven by the bus owner whenever the
data is valid on the bus.
Data Bus Busy:
Whenever the data is not valid on the bus with
DRDY# is deserted, DBSY# deasserted to hold the
bus.
Host Data Bus
Dynamic Bus Inversion: An active DBI# will
invert it’s corresponding data group signals.
DBI0# is referenced by HD[15:0]#
DBI1# is referenced by HD[31:16]#
DBI2# is referenced by HD[47:32]#
DBI3# is referenced by HD[63:48]#
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