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mitac 8599.pdf - tim.id.au

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8599 N/B Maintenance<br />

- Supports Graphic Window Size from 4MBytes to 512MBytes<br />

- Supports Pipelined Process in CPU-to-A.G.P. Access<br />

- Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance A.G.P. Controller Read/Write Performance<br />

- Supports PCI-to-PCI Br<strong>id</strong>ge Function for Memory Write from 33Mhz PCI Bus to A.G.P. device<br />

- Supports AGP 8X/4X Interface w/ Fast Write Transaction<br />

- Supports Hardware Enforced Coherence Outs<strong>id</strong>e GART Range for A.G.P. Transaction<br />

- Supports Data Bus Inversion and Calibration Cycle<br />

High Throughput SiS MuTIOL® 1G Interconnecting to SiS963 MuTIOL 1G Media I/O<br />

- Bi-directional 16 bit data bus<br />

- Perform 1GB/s bandw<strong>id</strong>th in 133MHz x 4 mode<br />

- Distributed arbitration strategy with long contiguous data streaming<br />

- Packet based, pipelining, and split transaction scheme<br />

Dedicated Isochronous Response Queue<br />

- Priority promotion for upstream Isochronous DMA memory read requests originated from real-<strong>tim</strong>e I/O device<br />

controllers, such as USB or <strong>au</strong>dio/modem<br />

- Dedicated Isochronous response queue serving Isochronous downstream transfers responsive to the memory read<br />

requests originated from real-<strong>tim</strong>e I/O device controllers, such as USB or <strong>au</strong>dio/modem. Offers privilege service<br />

to guarantee minimum latency & <strong>tim</strong>ely delivery<br />

High Performance & High Quality 3D Graphics Accelerator<br />

- Built-in a high performance 256-bit 3D engine<br />

15

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