CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

3-4 CAD/CAM/CAE—Electronic Design Automation Applications
Semiconductor vendors are in the best position to provide models, yet
they are reluctant to do so, as they feel it has limited impact on their
bottom-line financials. As proof, witness the recent Digital Equipment
Corporation/Cadence announcement on the Alpha chip model. While
Digital did lend its chip expertise, it is Cadence that is doing the sales
and marketing of the model.
Design Verification
Observing 1989 through 1991, digital design verification seem to be
as stagnant as schematic capture. However, there is an interesting
dynamic taking place underneath the top-line numbers. Gate-level
simulators are being swapped out by mixed-level simulators, which
correlates to the rapid growth in HDL-design entry tools.
Static timing analysis continues to stumble due primarily to technical
limitations. The tools to date have not been effective at separating
erroneous timing problems from actual timing issues.
Logic Syntiiesis
Qearly, logic synthesis has been the shining star for the past three
years. Synopsys is the dominant player in the market and rode the
synthesis wave into a wildly successful initial public offering in 1992.
Piggybacked onto the success of logic sjmthesis has been high-level
design entry and mixed-level simulation. In 1991 we saw a reduction
in the hypergrowth previously experienced as new offerings from a
slew of software vendors introduced pricing pressure and longer
product-evaluation cycles.
Test Automation
Test automation continues to bump along at the $30 to $40 million
range. Fault simulation took a big hit as its main industry sector,
Military and Aerospace, suffered from the "peace dividend."
Even with its lackluster performance, the test automation market has
been inundated with new products aimed at ATPG and test-logic synthesis.
The apparent lack of growth can be attributed to the following
factors:
• The tools and technologies offered to the market are expensive and
limited in scope.
• The tools and technologies offered to the market have thus far not
been well-integrated into the design flows and environments of
electronics manufacturers.
• The primary market has been ASIC design, and the average size of
ASIC design has just recently crossed the 20,000 gate mark. Thus,
the need for advanced tools has been limited.
• Except within the Military and Aerospace market, test traditionally
has not been built into the design methodologies of electronics
manufacturers.
October 12,1992 ©1992 Dataquest Incorporated CCAM-EDA-MT-9201