CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

Other advantages of top-down design tools
include an enhanced ability to perform trade-offs
in the areas of architectural design, chip size,
and circuit speed. In the absence of HDL-based
logic synthesis and supporting technologies,
engineers face the prospect of performing a significantly
greater nvunber of design iterations to
hone in on an optimal solution.
Migration from one chip technology to another,
commonly referred to as design remapping, is
yet another benefit of the technology. Examples
of remapping include the migration from one
process technology to another, such as remapping
a 1.2 micron CMOS design to 0.8 micron
CMOS implementation, and architectural
migration, such as remapping a field-programmable
gate array (FPGA) design to a maskprogrammable
gate array or cell-based IC.
Reusability: Exploiting tlie Power of
Top-Down Design
Dataquesf s research shows that electronics manufacturers
in both the United States and Japan
are aiming to reduce product design cycles by
20 to 30 percent between the current generation
and the next generation of electronic designs.
Reducing cycle time by this amount would not
be so daunting if the demands being placed on
design teams were not expanding so rapidly. For
instance, when asked to rank the three most
important fectors influencing a product's ability
to achieve market success, manufacturers cite
reducing time-to-market first, followed by
increasing functionality, and reducing costs.
Reconciling these three competing objectives
falls directiy upon the shoulders of the design
teams.
Given that the goal is reducing design time and
costs while significantly increasing fiinctionality,
it is vmrealistic to believe that simply improving
engineering talent and automation will be
enough to reduce product design time by 20 to
30 percent. Dataquesf believes that manufacturers
must also create a technology infrastructure
that supports large-scale reuse of existing
designs. Providing such technology is a clear
opportunity for EDA vendors. Today, 34 percent
of the electronics irom an average dectronic
product (built by North American electronics
manufacturers) is circviitry that has been reused
from an existing product. In Japan, the figure is
slightly higher, 37 percent. In our view, this level
CAD/CAM/CAE—Electronic Design Automation Applications
of reuse will not be enough to remain competitive.
Dataquesf believes that simultaneously
increasing product functionality, reducing cost,
and reducing design time (by 20 to 30 percent)
wiU require electronics maniifacturers to design
products comprising 45 to 55 percent of reused
circuitry (see Figure 1).
Integral to the reuse design methodology will be
the creation of logic functions described in an
HDL. These functions can be archived and
resynthesized in subsequent designs using the
various commercially available logic sjmthesis
packages.
We believe that the backbone of tomorrow's
technology advantage will depend heavily on an
electronics manufacturer's portfolio of intellectual
property or designs. Revise of these designs
will become critical as manufacturers strive to
fill the widening gap between design productivity
levels and the relentiess advancement of
semiconductor fabrication capabilities. Establishing
a hbrary (or "war chest") of designs that can
be readily reused (and perhaps enhanced) will
enable manufacturers to both reduce design time
and improve product qx;iality. Quality vdll
improve because the reused portion of the system
wiU have already vmdergone verification
during the previous product design cycle. Of
coiirse, these designs wiU require reverification
when integrated into the new product design.
Hidden within the reuse methodology is the
learning curve associated with archiving designs
and integrating the drcuitiy into the next-generation
product. Dataquesf s research indicates that
the methodology requires a 12- to 18-month
learning curve.
Akin to remapping, which was discussed earlier,
fovmdry independence is another key advantage
inherent to reusable HDL models. Because the
circuitry is described in a high-level generic language,
the models can be retargeted to almost
any tovmdry's fabrication process.
Dissecting the Top-Down Design Marlcet
Logic Synthesis
The logic synthesis market continues to
experience robust expansion, despite relatively
few vendors. Over the past three years, the
leading players in the EDA industry have
been tmable to moimt a seriotis threat to
Synopsys' market position. Sjmopsys has been
July 27, 1992 ©1992 Dataquest Incorporated CCAM-EDA-DP-9202