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CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

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IC Layout Market 5-3<br />

During the past three years, the increasing time-to-market pressure has<br />

caused semiconductor companies to re-evaluate their <strong>design</strong> process.<br />

The success of chip-set companies has been based on applying an<br />

ASIC <strong>design</strong> methodology to custom devices. Therefore it is not surprising<br />

that fueling the IC layout growth has been ASIC methodology<br />

<strong>design</strong> tools, primarily automatic placement and routing.<br />

Automatic Placement and Routing<br />

Automatic placement and routing tools fueled IC layout growth in<br />

1991, posting growth rates of 32 percent and 23 percent for gate-array<br />

and cell-based technologies, respectively. This trend is driven by chipset<br />

and more traditional semiconductor houses adopting ASIC <strong>design</strong><br />

techniques.<br />

Gate-array and cell-based placement and routing tools continue to<br />

gain ground on more traditional IC layout tools, APR now accounts<br />

for 29 percent of the IC layout market, and Dataquest anticipates that<br />

this trend will continue for the next three to five years.<br />

Design Verification<br />

Contributing $59 million to the IC layout market, <strong>design</strong> verification<br />

was essentially flat between 1990 and 1991. This is primarily due to<br />

the one-sided nature of this applicatiort Cadence continues to<br />

dominate this area with its Dracula product. While Mentor Graphics<br />

has been aggressively marketing its Checkmate product, it has been<br />

slow to gamer a large segment of the market. Cadence will continue<br />

to service its existing customers, but as a market, <strong>design</strong> verification<br />

will continue to remain flat until new technology is brought to bear<br />

on the problem.<br />

Module Generators and Compilers<br />

Module generators continue a disappointing performance, showing<br />

no growth between 1990 and 1991 posting only $12 million in 1991,<br />

versus $13 million in 1990. It has been an uphiU battle for EDA<br />

companies to establish a need within the <strong>design</strong>er's mind for this type<br />

of product. Cadence, which enjoys IC layout dominance, has been surprisingly<br />

ineffective in providing a successful product in this arena,<br />

which continues to be Mentor Graphics' strength with its GDT<br />

product.<br />

Cell compilers languish with its module generation brethren, posting<br />

an essentially flat 1991 at $14 million. Dataquest anticipated that this<br />

market would continue to remain flat for the foreseeable future in<br />

1991. Third-party suppliers of cell compilers find it difficult to work<br />

vrith ASIC companies that have typically bundled their proprietary<br />

cell compilers with their libraries.<br />

Shipments<br />

The year 1991 saw Asia becoming the largest consumer of IC layout<br />

tools by a wide margin (see Figure 5-3 and Table 5-1). This<br />

shoiild come as no surprise to those working in the semiconductor<br />

C<strong>CAM</strong>-EDA-MT-9201 ©<strong>1992</strong> Dataquest Incorporated October 12, <strong>1992</strong>

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