CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

CAD/CAM/CAE—Electronic Design Automation Applications
Figure 1
1991 North American HDL Market Segmentation
Others
(Nonproprietary)
(9.3%) v^^,,^
/ No Use \
/ of HDL \
I (22.9%) \
Y"""'^ Proprietary /
\ HDL /
\ (15.7%) /
VHDL \
(24.3%) \
Verilog g
HDL M
(27.8%) ^
Notes:
1. Segmentation de (ta are t>ased on
end-user survey results.
2. Segments reflect percentage of users.
Source: Dataquest (April 1992)
Historical and projected market share figures
published in April 1991 show worldwide
figures, as opposed to a regional segmentation.
At the worldwide level, our figures show that
the market shares of Verilog HDL and VHDL
were nearly equivalent This is based on our
estimate that Verilog HDL and VHDL's Norfli
American market shares were approximately
equal, whereas in Japan, Verilog HDL held a
significant edge; in Europe, a less exhaT:istive
study indicated that VHDL held a significant
advantage over Verilog HDL.
North American Outlook
Among the most significant issues facing EDA
software vendors and ASIC suppliers is determining
how the HDL landscape will shift over
the next three years. Dataquesf s most recent
studies shed light on the subject. Figure 3 shows
the projected market share of the various HDLs
in North America. The chart was generated by
Figure 2
1991 Japanese HDL Market Segmentation
UDUI
(0.2%)
Others
(Nonproprietary)
(6.2%)
Notes:
1. Segmentation data are based on
end-user survey results.
2. Segments reflect percentage of users.
oanoeia Source: Dataquest (April 1992) G2000619
surveying electronic design groups at over
250 different sites throu^out North America.
Engineers and managers were aslffid which HDL
they planned to use for their next-generation
design. The results show that an overwhelming
percentage plan to adopt VHDL.
Despite the strong response fevoring VHDL, it
is important to recognize that VHDL-based tools
will realize their market share potential only if
they fill fin the market's performance requirements,
The data in Figure 3 is simply a reflection
of the market's current thinking. Our
assumption underlying the data is that VHDL's
performance problems vriU be resolved and that
the ASIC libraries will be available for VHDL
tools. Most EDA vendors maintain that VHDLbased
tools will deliver the necessary performance
requirements, but users still complain
about VtS^L's slow simulation speed and excessive
memory requirements. We believe that these
performance issues will be resolved, given the
CW\M-EDA-DP-9201 ©1992 Dabquest Incoiporaled April 27, 1992