CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

IC Layout Market 5-5
possible to foresee the day when only extremely high volume standard
parts such as microprocessors and DRAMs will by designed
using fuU custom techniques.
Emerging Tool Opportunities
Dataquest believes that significant opportunity exists to bring new
technology to bear upon the design cycle problem, namely floorplanning
tools. Historically, advancement in the process for developing
ASIC has been in two distinct areas. The first area is the IC
layout section, where incremental improvements are made to APR
tools, including such advances as multilayer metal, more efficient
algorithms, and constraint-driven placement. The second area is in
the CAE arena, where great strides have been made in improving
the ASIC designer's productivity, by supplying him with top-down
design solutions. Yet little progress has been made in the communication
between these two areas, and currently the majority of
designs are transferred from the ASIC designer to the foxmdry
using a connectivity netlist and little else.
Dataquest believes that properly designed floorplarming tools have
a significant market potential. This wUl be the first time that IC
layout technology will be migrated toward the electronic system
designer. Floorplanners used in conjunction with a top-dov\m design
methodology can significantly improve the optimization of synthesis
tools, and improve first-pass success through back-end APR tools.
Additionally, improved timing estimation provided by floorplarmers
wfll enable the designer to design more aggressive systems.
For floorplanners to be successful, they must be target for the logic
designer. One often-cited flaw of existing proprietary floorplanners
is the fact that they require intimate knowledge of silicon design.
Other factors necessary for floorplarming success include a low
price point. Dataquest believes that a floorplanner priced in the
$15,000 to $30,000 range wUl have optimal acceptance.
Dataquest research shows that by 1996 there will be upwards of
20,000 designers using top-down design methodologies to develop
ASICs. A floorplarming tool is not the type of tool that will exist
on every designer's desk, but rather will be a focal point for
system-on-a-chip design. Therefore, the potential is for 2,000 seats
of floorplarming tools that provide the proper benefits. Additional
seats for floorplarming tools may be found in merchant IC vendors,
as they migrate toward ASIC design methodologies.
Regional Effects
Asia has been the catalyst for growth in the IC layout market. As
shown in Figure 5-5, Asia currently accounts for 50 percent of the consumption
of IC layout tools. Dataquest anticipates that this trend will
continue as more IC manufacturing and ASIC vendor power moves
eastward.
CCAIVI-EDA-MT-9202 ©1992 Dataquest Incorporated December 28,1992