CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

Figure 2
Historical and Projected Growth of Worldwide Logic Synthesis Market
Millions of Dollars
250-
200-
150-
100r
50-
@ FPGA/PLD
^ AS)C
Source: Dataquest (July 1992)
CAD/CAM/CAE—Electronic Design Automation Applications
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^ ^ T 1 r
1989 1990 1991 1992 1993 1994 1995 1996
HDL and Next Generation Design Entry
Opportunities
Dataquesf s research shows that the traditional
gate-level schematic entry market has reached
maturity and is moving into a period of
decline. The technology has become a commodity
and the market is virtually saturated,
although the replacement and low-end markets
remain strong. The gate-level schematic entry
market grew a negligible amount between
1989 and 1990. Preliminary estimates for 1991
suggest figures similar to that of 1990. This
should come as no surprise to companies
supplying products to this sector. Gate-level
schematic entry is "last generation" technology
that is used primarily for less complex
designs. Nearly all of the schematic entry
systems currently on the market have been
geared toward bottom-up design, as opposed
to top-down design. We believe that the gatelevel
schematic capture market, which has
remained flat over the pcist few years, will
begin to shrink in size (see Figure 3).
Fast on the heels of the schematic entry market
has been the HDL entry opportvmity,
which includes the text editors, debuggers, and
user interface software needed for designing
with languages such as VHDL and Verilog
HDL. Segmenting the design entry market
reveals that the HDL entry market is indeed
G2001035
experiencing rapid expansion and, in our view,
will continue to exhibit strength over the next
two to three years. In fact, some designers
and electronics manufacturers have completely
discarded schematic entry and have begun
reljdng exclxisively on HDL for design entry.
Despite the trend, we believe that this is
somewhat of an aberration. Dataquest projects
that most designers wiU use a combination of
HDL and graphical entry in the future.
In our view, designers will gravitate toward
next-generation design entry environments that
combine high-level graphical capture, HDLbased
entry, gate-level schematic entry and
even traditioiial entry technologies for programmable
logic devices (PLDs) and FPGAs such
as Boolean equations, truth tables, and state
machine bubble diagrams. In other words, we
believe that the mainstream design market will
want a heterogeneous design environment.
Some recently introduced first-generation systems
address pieces of the heterogeneous
reqtiirement.
The marketplace clearly prefers graphical entry,
as demonstrated by how HDL entry is ranked
in comparison to graphical entry. On a scale
of one to five, witii five being "most important"
and one being "least important," a
statistically valid sample of users assign a
value of 4.1 (mean score) to graphical
July 27,1992 ©1992 Dataquest Incorporated CCAM-EDA-DP-9202