CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

CAE Market 3-7
Figure 3-6
Worldwide Logic Sjmthesis Software Market History and Forecast
Millions of Dollars
180-
160-
140-
120-
100-
80-
60-
40-
20-
0
1989 1990 1991 1992 1993 1994 1995 1996
Source: Dataquest (December 1992)
gate-level schematic capture market will experience a steady decline
during the next five years, as shown in Figure 3-7.
Fast on the heels of the schematic entry market is the technology that
is replacing it, namely, HDL entry. This category of tools includes text
editors, source debuggers, syntax checkers, and user interface software
needed for designing with VHDL and Verilog HDL. Our research indicates
that this segment is experiencing rapid expansion and wUl continue
to exhibit strength during the next two to three years. As a case
in point, certain electronic system companies now design solely in
HDL. However, Dataquest believes that a graphical representation is
the most intuitive way to describe a concurrent system, and most
designers use a combination of graphics and textual entry.
The graphical capabilities of next-generation entry products will be
integral to iniproving design productivity. This next generation of
graphic design-entry technology will enable designers to use a building
block approach whereby the individual blocks are a combination
of VLSI functions described in HDL, compilers, and hardwired core
fimctions.
With HDL blocks, designers will reuse and modify existing blocks for
subsequent designs, as well as create new blocks to meet the demands
of the project. The HDL functions will also be represented as graphical
blocks, but the designer will be given the freedom to quickly access
and modify the blocks' internal HDL.
Revenue
(PLD/
FPGA)
Revenue
(ASIC)
G2001Se7
CCAM-EDA-MT-9202 ©1992 Dataquest Incorporated December 28,1992