CAD/CAM/CAE : electronic design automation, 1992 - Archive Server

The Design Process 3-5
While there is a definite need for fault coverage, it is not free. There is
a significant penalty in both cost and speed for increasing the testability
of a design. To detemune how much electronic designers are
willing to pay for increased testability, Dataquest cross-correlated the
targeted fault coverage a designer wishes to achieve, with the penalty
he is willing to pay in both speed and density. Figure 3-18 shows the
results of this analysis. In general, designers recognize that they will
have to pay an increasing penalty in speed and cost to achieve higher
levels of testability. Particularly important, however, is the fact that the
design engineer will more readily pay for an increased component
cost than a slower system speed.
Systems Integration and Verification
The systems integration and verification portion of the design cycle
consumes the same amount of time as the test development phase.
According to users, there are few ways to approach this problem.
Currently, there exists three methods of verifying the integrity of a
system:
• Simulation of critical parts
• Full system simulation
• Breadboarding
Figures 3-19, 3-20, and 3-21 show the current and anticipated future
usage of each type of verification technique. Clearly, users have a
strong desire to move away from breadboarding and toward
full system-level simulation. However, this must be tempered with
the ability of the EDA vendors to supply a valid solution. The
following factors may retard the implementation of full-system
simulation:
• Increased system complexity
• Simulation capacity
• Simulation speed
• Model availability
Dataquest believes that three years ago, user's response to planned
usage of system verification would have been quite similar. The
"Holy Grail" of full-system simulation continues to be sought after
by the large majority of users, yet only a minority have been successful
in obtaining the goal. Dataquest anticipates that breadhoarding
will continue to play an active role in system verification,
and new advanced breadboarding capabilities using programmable
technology will fuel the longevity of breadboarding.
Prototype Debugging
Prototj^e debugging consumes approximately 17 percent of the system
design cycle worldwide. During this phase of the design process,
two type of errors may be imcovered in the system: timing violations
and functional violations. To gauge which type of design error was
more problematic, Dataquest asked electronic designers which type of
designer error consumed more time after the prototj^e was received.
CCAM-EDA-UW-9201 ©1992 Dataquest Incorporated November 30, 1992