Hardware Manual - RTD Embedded Technologies, Inc.

This register sets up the trigger mode and the method by which A/D conversions are performed (conversion
select bits).
Trigger Mode Register, performing A/D conversions (bits 0 and 1):
00 = Conversions are controlled by reading BA + 0x06h (Start Convert).
01 = Conversions are controlled by the internal or an external pacer clock.
10 = Conversions are controlled by the burst clock.
11 = Conversions are controlled by a digital interrupt.
Trigger Mode Register, selecting the start trigger source (bits 2 through 4):
000 = The pacer clock is started by reading BA + 0x06h (Start Convert).
001 = The pacer clock is started by an external trigger (TRIGGER IN, CN3, pin 39).
010 = The pacer clock is started by a digital interrupt.
011 = The pacer clock is started when the output of User TC Counter 1 reaches 0.
100 = Reserved.
101 = Reserved.
110 = Reserved.
111 = The pacer clock runs as long as the TRIGGER IN line is held high or low, depending on the polarity bit setting at
BA + 0x06h, bit 12.
Trigger Mode Register, selecting the stop trigger source (bits 5 through 7):
000 = The pacer clock is stopped by reading BA + 0x06h (Start Convert).
001 = The pacer clock is stopped by an external trigger (TRIGGER IN, CN3, pin 39).
010 = The pacer clock is stopped by a digital interrupt.
011 = The pacer clock is stopped by the sample counter (count reaches 0).
The following four stop trigger sources programmed at these bits provide about triggering, where data is
acquired from the time the start trigger is received, and continues for a specified number of samples after the
stop trigger is received. The A/D sample counter sets the number of samples taken after the stop trigger is
received.
100 = The A/D sample counter takes a specified number of samples after a read at BA + 0x06h (Start Convert).
101 = The A/D sample counter takes a specified number of samples after an external trigger is received.
110 = The A/D sample counter takes a specified number of samples after a digital interrupt occurs.
111 = The A/D sample counter takes a specified number of samples after the output of User TC Counter 1 reaches 0.
Trigger Mode Register, bits 8 through 13:
Bit 8:
Bit 9:
Bits
10/11:
Bit 12:
Bit 13:
Selects a 16-bit or 32-bit onboard pacer clock (Clock TC Counter 0 or 1 output). When a trigger is used to start
the pacer clock, there is some delay between the time the trigger occurs and the time the next pacer clock
pulse starts an A/D conversion. For a 16-bit clock, this jitter is 125 ns, max. For a 32-bit clock, this jitter
depends on the value programmed into the first divider and can be much greater than 125 ns. (See Chapter 5.)
Selects the internal pacer clock, which is the output of Clock TC Counter 0 or 1, or an external pacer clock
routed onto the board through CN3, pin 41. The max. pacer clock rate supported by the board is 500 kHz.
Select the burst mode trigger. Bursts can be triggered through software (Start Convert command), by the
pacer clock, by an external trigger, or by a digital interrupt.
Sets the external trigger to occur on the positive-going or negative-going edge of the pulse.
When set to single cycle, a trigger will initiate one conversion cycle and then stop, regardless of whether the
trigger line is pulsed more than once; when set to repeat, a new cycle will start each time a trigger is received,
and the current cycle has been completed. Triggers received while a cycle is in progress will be ignored.
BDM-610010034 Rev C Chapter 4: I/O Mapping 45