Hardware Manual - RTD Embedded Technologies, Inc.

38 DM6425HR dataModule BDM-610010034 Rev C
BA + 0x02h (2): Read Status/Program Control Register (Read/Write)
16-bit Operation.
Status Register (read): Bits 15 and 9 are reserved.
A read provides the status bits defined below. Starting with bit 0, these status bits show:
Bit 0:
Bit 1:
Bit 2:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IRQ 2 Status
0 = no IRQ
1 = IRQ
IRQ 1 Status
0 = no IRQ
1 = IRQ
Digital Input FIFO Full
0 = FIFO full
1 = FIFO not full
Digital Input FIFO Half Full
0 = FIFO half full
1 = FIFO not half full
Digital Input FIFO Empty
0 = FIFO empty
1 = FIFO not empty
About Trigger Flag
0 = in progress
1 = completed
Pacer Clock Gate Flag
0 = pacer clock off
1 = pacer clock on
Goes high when there is something in the A/D sample buffer (FIFO).
Goes low when the sample buffer is full.
Goes high and halts A/D conversions when the sample buffer is full (this is useful whenever you are emptying
the buffer at a slower rate than you are taking data). A clear FIFO written to BA + 0x00h (bit 1 set high)
clears the sample buffer and this flag.
A/D FIFO Full Flag
0 = FIFO full
1 = FIFO not full
A/D Halt Flag
0 = A/D enabled
1 = A/D disabled
First DMA Flag (for dual-channel DMA)
0 = DMA not done on first channel
1 = DMA done on first channel
Burst Clock Gate Flag
0 = burst clock off
1 = burst clock on
End-of-Convert Status
0 = converting
1 = not converting
A/D DMA Done Flag
0 = DMA not done
1 = DMA done
A/D FIFO Empty Flag
0 = FIFO empty
1 = FIFO not empty