Hardware Manual - RTD Embedded Technologies, Inc.

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Defining the I/O Map Tables 6 and 7 provide the DM6425HR read/write registers. As shown, the board occupies 32 consecutive I/O port locations. Because of the 16-bit structure of the AT bus, every other address location is used. <strong>RTD</strong>’s programming structure uses the 16-bit command for reading/writing all locations except for programming the 8254 and digital lines. These require 8-bit read/write operations. The base address (BA) can be selected using the BASE ADDR jumper (J7) as described in Chapter 2, DM6425HR Module Settings. This switch can be accessed without removing the module from the stack. The following sections describe the register contents of each address used in the I/O map. BA = base address. 30 DM6425HR dataModule BDM-610010034 Rev C
BDM-610010034 Rev C Chapter 4: I/O Mapping 31 BA + Offset hex (dec) Table 6 DM6425HR Read Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00h (0) Reserved Clear DAC1 0x02h (2) Reserved IRQ2 Status 0x04h (4) 0x06h (6) Sign Extension IRQ1 Status Digin FIFO Full Digin FIFO Half Full Clear DAC2 Digin FIFO Empty Clear DAC3 Reserved A/D Data Clear DAC4 About Trig Flag Clear IRQ2 Pacer Clk Gate Flag Start Conversion Clear IRQ1 Burst Clk Gate Flag Clear Digin FIFO First DMA Done Flag Reset CGT A/D DMA Done 0x0Ah (10) Reserved Port 0 Digital Input FIFO 0x0Eh (14) Software Trigger for Loading Sample Counter 0x10h (16) Base + 0x02h Dependency (bits 6–5) Reserved Clear CGT EOC Status Timer 0 LSB/MSB Value Counter 0 LSB/MSB Value 0x12h (18) Reserved Timer 1 LSB/MSB Value Counter 1 LSB/MSB Value 0x14h (20) Reserved Timer 2 LSB/MSB Value Counter 2 LSB/MSB Value 0x18h (24) Reserved Digital I/O Port 0 Value 0x1Ah (26) Reserved Digital I/O Port 1 Value 0x1Ch (28) Base + 0x1Eh Dependency (bits 1–0) Reserved Reserved Reserved Reserved 0x1Eh (30) Reserved Port 0 Strobe Status Port 0 Digital IRQ Status Port 0 Dig Sample Clk Select Port 0 Clear Digital IRQ Status Flag Port 0 Direction Value Port 0 Mask Value Port 0 Compare Value Port 0 Digital IRQ Enable Port 0 Digital IRQ Mode Clear A/D DMA Done Flag A/D Halt Flag Port 1 Direction Clear A/D FIFO A/D FIFO Full A/D Markers Clear Board A/D FIFO Empty Port 0 Register Select
Page 1 and 2: DM6425HR 32-Channel, 500 kHz PC/104
Page 3 and 4: DM6425 32-Channel, 500 kHz PC/104 d
Page 5 and 6: Table of Contents Chapter 1 Introdu
Page 7 and 8: A/D Conversion Modes . . . . . . .
Page 9 and 10: D/A Calibration. . . . . . . . . .
Page 11 and 12: Chapter 1 Introduction The DM6425HR
Page 13 and 14: DM6425HR Ordering Information The D
Page 15 and 16: Features The DM6425HR is a 12-bit,
Page 17 and 18: Analog-to-Digital Conversion The DM
Page 19 and 20: 8254 Timer/Counters Two 8254 progra
Page 21 and 22: For More Information This manual an
Page 23 and 24: Chapter 2 DM6425HR Module Settings
Page 25 and 26: JS1 JS2 JS3 JS4 Figure 6 DM6425HR S
Page 27 and 28: Base Address Jumper (Factory Settin
Page 29 and 30: Chapter 3 Installing the dataModule
Page 31 and 32: Installation Considerations Conside
Page 33 and 34: External I/O Connections Figure 13
Page 35 and 36: Connecting the Analog Input Pins Th
Page 37 and 38: I/O CONNECTOR (CN3) SIGNAL SOURCE 1
Page 39: Chapter 4 I/O Mapping This chapter
Page 43 and 44: BDM-610010034 Rev C Chapter 4: I/O
Page 53 and 54: Load Channel-Gain Table in Channel-
Page 55 and 56: This register sets up the trigger m
Page 57 and 58: BA + 0x0Ah (10): Digital Input FIFO
Page 59 and 60: BA + 0x18h (24): Digital I/O Port 0
Page 61 and 62: BA + 0x1Eh (30): Digital IRQ Status
Page 63 and 64: BA + 0x408h (1032): DAC3 Update Reg
Page 65 and 66: BA + 0x41Ch (1052): Read/Program Po
Page 67 and 68: BA + 0x800h/801h (2048/2049): Board
Page 69 and 70: Setting or clearing more than one b
Page 71 and 72: Chapter 5 A/D Conversions This chap
Page 73 and 74: Programming Channel, Gain, Input Ra
Page 75 and 76: Pause Bit Bit 11 is used as a pause
Page 77 and 78: With BA + 0x00h, bits 1 and 0 set t
Page 79 and 80: TO A/D CONVERTER A/D CONVERSION SEL
Page 81 and 82: Trigger Repeat Function Bit 13 in t
Page 83 and 84: Programmable Burst In this mode, a
Page 85 and 86: Voltage values for each bit will va
Page 87 and 88: Programming Steps The pacer clock i
Page 89 and 90: Using the Sample Counter to Create
Page 91 and 92:
Mathematical formula for calculatin
Page 93 and 94:
Chapter 6 Data Transfers Using DMA
Page 95 and 96:
Allocating a DMA Buffer When using
Page 97 and 98:
Setting the DMA Page Register Oddly
Page 99 and 100:
Programming the DM6425HR for DMA On
Page 101 and 102:
Chapter 7 Interrupts This chapter e
Page 103 and 104:
CLOCK DIGITAL INPUT IRQ OUT Figure
Page 105 and 106:
If you find yourself intimidated by
Page 107 and 108:
Restoring the Startup IMR and Inter
Page 109 and 110:
Chapter 8 D/A Conversions This chap
Page 111 and 112:
Chapter 9 Timer/Counters This chapt
Page 113 and 114:
Each timer/counter has two inputs,
Page 115 and 116:
Chapter 10 Digital I/O This chapter
Page 117 and 118:
When using event interrupts, you ca
Page 119 and 120:
Appendix A Example Programs This ap
Page 121 and 122:
Special Considerations When manipul
Page 123 and 124:
Appendix B Calibration This appendi
Page 125 and 126:
A/D Calibration Two procedures are
Page 127 and 128:
Below is a table listing the ideal
Page 129 and 130:
Appendix C Specifications This appe
Page 131 and 132:
Table 11 DM6425HR Specifications (c
Page 133 and 134:
Appendix D I/O Connector Pin Assign
Page 135 and 136:
Mating Connector Part Numbers Manuf
Page 137 and 138:
Appendix E IDAN Dimensions and Pino
Page 139 and 140:
IDAN-DM6425HR-62S External I/O Conn
Page 141 and 142:
IDAN-DM6425HR-68S External I/O Conn
Page 143 and 144:
Appendix F Limited Warranty RTD Emb
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