Hardware Manual - RTD Embedded Technologies, Inc.

BA + 0x08h (8): Program IRQ Source and Channel (Write)
16-bit Operation.
Interrupt Register:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IRQ2 Channel Select
000 = disabled
001 = IRQ3
010 = IRQ5
011 = IRQ9
100 = IRQ10
101 = IRQ11
110 = IRQ12
111 = IRQ15
IRQ2 Source Select
IRQ1 Channel Select
00000 = A/D sample counter 000 = disabled
00001 = A/D start convert 001 = IRQ3
00010 = A/D end-of-convert 010 = IRQ5
00011 = A/D write FIFO
011 = IRQ9
00100 = A/D FIFO half full 100 = IRQ10
00101 = A/D DMA done 101 = IRQ11
00110 = reset channel-gain table 110 = IRQ12
00111 = pause channel-gain table 111 = IRQ15
01000 = external pacer clock
01001 = external trigger
01010 = digital interrupt
01011 = User TC Counter 0 out
01100 = User TC Counter 0 out inverted
01101 = User TC Counter 1 out
01110 = digital input FIFO half full
01111 = digital input write FIFO
10000 = digital interrupt port2/3
10001 = analog threshold
10010 = external interrupt 1
10011 = external interupt 2
IRQ1 Source Select
00000 = A/D sample counter
00001 = A/D start convert
00010 = A/D end-of-convert
00011 = A/D write FIFO
00100 = A/D FIFO half full
00101 = A/D DMA done
00110 = reset channel-gain table
00111 = pause channel-gain table
01000 = external pacer clock
01001 = external trigger
01010 = digital interrupt
01011 = User TC Counter 0 out
01100 = User TC Counter 0 out inverted
01101 = User TC Counter 1 out
01110 = digital input FIFO half full
01111 = digital input write FIFO
10000 = digital interrupt port2/3
10001 = analog threshold
10010 = external interrupt 1
10011 = external interupt 2
This register programs the software selectable interrupt source and channel. The IRQ circuitry is driven by an
open collector device which is turned off when the IRQ channel is set to disable. The IRQ sources are:
A/D sample counter: an interrupt is generated when the A/D sample counter count reaches 0.
A/D start convert:
an interrupt is generated when a conversion is started.
A/D end-of-convert:
an interrupt is generated when an end-of-convert is issued by the A/D converter.
A/D write FIFO:
an interrupt is generated when data is written into the A/D FIFO.
A/D FIFO half full:
an interrupt is generated when the A/D FIFO is half-full.
A/D DMA done:
an interrupt is generated when the A/D DMA done flag goes high.
Reset channel-gain table: an interrupt is generated when the channel-gain table resets to the beginning.
Pause channel-gain table: an interrupt is generated when a pause occurs in the channel-gain table.
External pacer clock:
an interrupt is generated when the external pacer clock line is pulsed.
External trigger:
an interrupt is generated when the external trigger line is pulsed.
Digital interrupt:
an interrupt is generated when an advanced digital interrupt occurs.
User TC Counter 0 out: an interrupt is generated when user TC Counter 0’s count reaches 0.
User TC Counter 0 out inverted:an interrupt is generated when user TC Counter 0’s count reaches 0
(useful for frequency counting).
User TC Counter 1 out: an interrupt is generated when user TC Counter 1’s count reaches 0.
Digital input FIFO half full: an interrupt is generated when the Digital Input FIFO is half-full.
Digital input write FIFO: an interrupt is generated when data is written into the Digital Input FIFO.
46 DM6425HR dataModule BDM-610010034 Rev C