Hardware Manual - RTD Embedded Technologies, Inc.

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Analog Trigger The DM6425HR has a unique feature that enables it to work like a digital oscilloscope. The board has the ability to trigger when a certain voltage level is reached on any one of the analog inputs. A register threshold value entered by the user has a built-in hysteretic span for noise, which depends on the front end range. This value is approximately 39 mV for the 0 to +10 V and ± 5 V ranges, and approximately 78 mV for the ± 10 V range. The hysteresis range is split above and below the threshold value. In essence, the threshold value is reduced from twelve bits to eight bits as a filter for environmental noise that might occur. The user also selects which front end channel to use as a trigger and whether to trigger on a signal that is greater than or less than or equal to the threshold value. Depending on the mode (Channel Gain Latch or Channel Gain Table), the board will then take A/D samples without writing them to the FIFO until the threshold value is reached by the appropriate channel. An onboard one shot is then triggered, which allows samples to be written into the FIFO. When using this board feature it is important to follow a sequence of driver command functions to avoid potential false triggers. Source code should address the following register sequence: 1. Disable A/D FIFO writes BA + 0x02h, bit 10. 2. Set Threshold Value to include trigger channel and >, < bit (BA + 0x410h). 3. Clear A/D FIFO BA + 0x00h, bit 2. 4. Start A/D conversions. (This depends on which trigger mechanism is used.) 5. Set Use Threshold bit (BA + 0x410h, bit 14). It is important that the Use Threshold bit (BA + 0x410h, bit 14) and the rest of the register (channel, threshold value, and boolean comparison) are written to in a 2-step procedure as described above. This will allow values to be set up within the register before enabling, which in turn will protect against false triggers. Below is a table showing some of the possible threshold values as related to range and polarity Table 8 Analog Trigger Threshold Values Threshold Value (hex) ± 5 V ± 10 V 0 to +10 V 0 0.000 0.000 0.000 1 0.039 0.078 0.039 F 0.586 1.172 0.586 1F 1.211 2.422 1.211 2F 1.836 3.672 1.836 3F 2.461 4.922 2.461 4F 3.086 6.172 3.086 5F 3.711 7.422 3.711 6F 4.336 8.672 4.336 7F 4.961 9.922 4.961 8F –4.414 –8.828 5.586 9F –3.789 –7.578 6.211 FF –0.039 –0.078 9.961 80 DM6425HR dataModule BDM-610010034 Rev C
Mathematical formula for calculating threshold voltages: ± 5 V ± 10 V 0 to +10 V Positive (Hex Value) * (10 / (Gain * 256)) Negative [(Hex Value) * (10 / Gain * 256))] – (9.961 / Gain) (Hex Value) * (20 / (Gain * 256)) [(Hex Value) * (20 / (Gain * 256))] – (19.922 / Gain) (Hex Value) * (10 / (Gain * 256)) — BDM-610010034 Rev C Chapter 5: A/D Conversions 81
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DM6425HR 32-Channel, 500 kHz PC/104
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DM6425 32-Channel, 500 kHz PC/104 d
Page 5 and 6:
Table of Contents Chapter 1 Introdu
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A/D Conversion Modes . . . . . . .
Page 9 and 10:
D/A Calibration. . . . . . . . . .
Page 11 and 12:
Chapter 1 Introduction The DM6425HR
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DM6425HR Ordering Information The D
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Features The DM6425HR is a 12-bit,
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Analog-to-Digital Conversion The DM
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8254 Timer/Counters Two 8254 progra
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For More Information This manual an
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Chapter 2 DM6425HR Module Settings
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JS1 JS2 JS3 JS4 Figure 6 DM6425HR S
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Base Address Jumper (Factory Settin
Page 29 and 30:
Chapter 3 Installing the dataModule
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Installation Considerations Conside
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External I/O Connections Figure 13
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Connecting the Analog Input Pins Th
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I/O CONNECTOR (CN3) SIGNAL SOURCE 1
Page 39 and 40: Chapter 4 I/O Mapping This chapter
Page 41 and 42: BDM-610010034 Rev C Chapter 4: I/O
Page 53 and 54: Load Channel-Gain Table in Channel-
Page 55 and 56: This register sets up the trigger m
Page 57 and 58: BA + 0x0Ah (10): Digital Input FIFO
Page 59 and 60: BA + 0x18h (24): Digital I/O Port 0
Page 61 and 62: BA + 0x1Eh (30): Digital IRQ Status
Page 63 and 64: BA + 0x408h (1032): DAC3 Update Reg
Page 65 and 66: BA + 0x41Ch (1052): Read/Program Po
Page 67 and 68: BA + 0x800h/801h (2048/2049): Board
Page 69 and 70: Setting or clearing more than one b
Page 71 and 72: Chapter 5 A/D Conversions This chap
Page 73 and 74: Programming Channel, Gain, Input Ra
Page 75 and 76: Pause Bit Bit 11 is used as a pause
Page 77 and 78: With BA + 0x00h, bits 1 and 0 set t
Page 79 and 80: TO A/D CONVERTER A/D CONVERSION SEL
Page 81 and 82: Trigger Repeat Function Bit 13 in t
Page 83 and 84: Programmable Burst In this mode, a
Page 85 and 86: Voltage values for each bit will va
Page 87 and 88: Programming Steps The pacer clock i
Page 89: Using the Sample Counter to Create
Page 93 and 94: Chapter 6 Data Transfers Using DMA
Page 95 and 96: Allocating a DMA Buffer When using
Page 97 and 98: Setting the DMA Page Register Oddly
Page 99 and 100: Programming the DM6425HR for DMA On
Page 101 and 102: Chapter 7 Interrupts This chapter e
Page 103 and 104: CLOCK DIGITAL INPUT IRQ OUT Figure
Page 105 and 106: If you find yourself intimidated by
Page 107 and 108: Restoring the Startup IMR and Inter
Page 109 and 110: Chapter 8 D/A Conversions This chap
Page 111 and 112: Chapter 9 Timer/Counters This chapt
Page 113 and 114: Each timer/counter has two inputs,
Page 115 and 116: Chapter 10 Digital I/O This chapter
Page 117 and 118: When using event interrupts, you ca
Page 119 and 120: Appendix A Example Programs This ap
Page 121 and 122: Special Considerations When manipul
Page 123 and 124: Appendix B Calibration This appendi
Page 125 and 126: A/D Calibration Two procedures are
Page 127 and 128: Below is a table listing the ideal
Page 129 and 130: Appendix C Specifications This appe
Page 131 and 132: Table 11 DM6425HR Specifications (c
Page 133 and 134: Appendix D I/O Connector Pin Assign
Page 135 and 136: Mating Connector Part Numbers Manuf
Page 137 and 138: Appendix E IDAN Dimensions and Pino
Page 139 and 140: IDAN-DM6425HR-62S External I/O Conn
Page 141 and 142:
IDAN-DM6425HR-68S External I/O Conn
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Appendix F Limited Warranty RTD Emb
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